DS90UB926Q-Q1: Condition Lock pin assert Low

Tomohiro Nagasawa58

Expert 1570 points

Part Number: DS90UB926Q-Q1

Dear support team

In my customer, there is a problem that the LVDS input image from Deserializer is black, and the LOCK pin is LOW.

Could you teach the condition that LOCK pin becomes low?

.
(For example, the jitter of PCLK is more than ○%)

Regards

Tomohiro Nagasawa

over 6 years ago

0 Darryl Jeong over 6 years ago

TI__Expert 4210 points

Hi Nagasawa-san,

I think your question is what condition will cause the LOCK pin on the DS90UB926 to go LOW correct?

Can you give me some basic information before we start talking about jitter?

1) What is the serializer? e.g DS90UB925?, DS90UB927?

2) What is the input clock frequency?

3) How long is the FPD3 interface cable?

4) Is this a single DS90UB926 showing an issue? or multiple units?

5) Does the LOCK pin toggle HIGH and LOW or absolutely stuck LOW? Did you measure with an oscilloscope?

0 Darryl Jeong over 6 years ago in reply to Darryl Jeong

TI__Expert 4210 points

Hi Nagasawa-san,

Is the problem resolved?

0 Tomohiro Nagasawa58 over 6 years ago in reply to Darryl Jeong

Expert 1570 points

Hi Darryl-san

Sorry for delay response.
First of all, the customer is re-examining another cause, so we will contact you if there is progress.

Regards
Tomohiro Nagasawa

0 Darryl Jeong over 6 years ago in reply to Tomohiro Nagasawa58

TI__Expert 4210 points

Hi Nagasawa-san,

No problem, at your convenience.

Can you please close this inquiry and reopen when you are ready?

Also, please have the answers to the questions I posted earlier if you still have the same issue when you reopen.

Regards,

Darryl

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DS90UB926Q-Q1: Condition Lock pin assert Low