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DP83867CS: low jitter

Jim Laser
Prodigy 55 points
Part Number: DP83867CS

The SNLS504B datasheet for this part simply states that, "It has low jitter". Do you have any numerical data to characterize what is meant by "low"? For instance, assuming data coming into the PHY has a known jitter from its source, what max additional jitter should be expected from the PHY itself as the data is transmitted out onto the network?

Thank you,
Jim

  • 0
    TI__Mastermind 18425 points
    Hi Jim,

    The statement about low jitter relates to the output 25MHz clock which is used for synchronization or for clocking a 2nd DP83867. That statement is not related to the transmit Jitter on the PHY cable side output. The output on the cable side (MDI) has specific jitter requirements as per IEEE standards and DP83867 can meet those requirements.

    Although we do not publish jitter numbers for the output clock, we can say that the output clock of one DP83867 can be used as a reference clock input (25MHz) for a 2nd DP83867. This assumes that the 1st DP83867 has a clock input that meets the datasheet requirement.

    -Regards
    Aniruddha