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Original question:
DS90UB954-Q1EVM: Data type packet header field is not as expected after deserialization
Part Number: DS90UB964-Q1
hello team
When DS90UB964 used Internally Generated FrameSync and find buffer_ERROR. It seem the occure overflow. Does 964 have registers check the the root cause or do you give some comment that i can debug to find the root cause? thanks
Hi Xiao,
Buffer error means your input is higher than your output. Try to set the CSI output rate higher or reduce your CSI input rate and see if it resolves your issue.
Best,
Jiashow
Hello Jiashow
When not use internal FrameSync, the buffer error is diappear. Attached is the register setup. So could you give more comment about it?
[ 22.938236] == 964 read Reg[0xF0] = 0x5F [ 22.938919] == 964 read Reg[0xF1] = 0x55 [ 22.939581] == 964 read Reg[0xF2] = 0x42 [ 22.940229] == 964 read Reg[0xF3] = 0x39 [ 22.940875] == 964 read Reg[0xF4] = 0x36 [ 22.941523] == 964 read Reg[0xF5] = 0x34 [ 39.425403] == 964 Write Reg[0x10] = 0x81 [ 39.425928] == 964 Write Reg[0x11] = 0x85 [ 39.426465] == 964 Write Reg[0x12] = 0x89 [ 39.426968] == 964 Write Reg[0x13] = 0x8D init_port RX0 [ 39.427478] == 964 Write Reg[0x20] = 0xE0 [ 39.427979] == 964 Write Reg[0x4C] = 0x01 [ 39.428479] == 964 Write Reg[0x58] = 0x58 [ 39.428978] == 964 Write Reg[0x7C] = 0xC1 [ 39.429476] == 964 Write Reg[0x70] = 0x1E [ 39.429976] == 964 Write Reg[0x6D] = 0x7F [ 39.430473] == 964 Write Reg[0xBC] = 0x00 init_port RX1 [ 39.430982] == 964 Write Reg[0x20] = 0xD0 [ 39.431480] == 964 Write Reg[0x4C] = 0x12 [ 39.431979] == 964 Write Reg[0x58] = 0x58 [ 39.432476] == 964 Write Reg[0x7C] = 0xC1 [ 39.432975] == 964 Write Reg[0x70] = 0x5E [ 39.435155] == 964 Write Reg[0x6D] = 0x7F [ 39.435671] == 964 Write Reg[0xBC] = 0x00 init_port RX2 [ 39.436248] == 964 Write Reg[0x20] = 0xB0 [ 39.436761] == 964 Write Reg[0x4C] = 0x24 [ 39.437271] == 964 Write Reg[0x58] = 0x58 [ 39.437776] == 964 Write Reg[0x7C] = 0xC1 [ 39.438282] == 964 Write Reg[0x70] = 0x9E [ 39.438789] == 964 Write Reg[0x6D] = 0x7F [ 39.439296] == 964 Write Reg[0xBC] = 0x00 init_port RX3 [ 39.439812] == 964 Write Reg[0x20] = 0x70 [ 39.440323] == 964 Write Reg[0x4C] = 0x38 [ 39.440826] == 964 Write Reg[0x58] = 0x58 [ 39.441330] == 964 Write Reg[0x7C] = 0xC1 [ 39.441835] == 964 Write Reg[0x70] = 0xDE [ 39.442339] == 964 Write Reg[0x6D] = 0x7F [ 39.442844] == 964 Write Reg[0xBC] = 0x00 [ 39.444877] == 964 Write Reg[0x32] = 0x01 [ 39.445395] == 964 Write Reg[0x1F] = 0x02 [ 39.445910] == 964 Write Reg[0x33] = 0x11 [ 39.446495] == 964 Write Reg[0x20] = 0x00 // [ 39.447009] == 964 Write Reg[0x4C] = 0x01 [ 39.447682] == 964 read Reg[0x4D] = 0x13 [ 39.448195] == 964 Write Reg[0x4C] = 0x12 [ 39.448867] == 964 read Reg[0x4D] = 0x40 [ 39.449379] == 964 Write Reg[0x4C] = 0x24 [ 39.450049] == 964 read Reg[0x4D] = 0x80 [ 39.450563] == 964 Write Reg[0x4C] = 0x38 [ 39.451237] == 964 read Reg[0x4D] = 0xC0 // framesync [ 39.451751] == 964 Write Reg[0x17] = 0x93 [ 39.452268] == 964 Write Reg[0x0F] = 0x00 [ 39.452779] == 964 Write Reg[0x4C] = 0x01 [ 39.454640] == 964 Write Reg[0x6E] = 0x88 [ 39.455138] == 964 Write Reg[0x6F] = 0x9A [ 39.455632] == 964 Write Reg[0x4C] = 0x12 [ 39.456127] == 964 Write Reg[0x6E] = 0x88 [ 39.456635] == 964 Write Reg[0x6F] = 0x9A [ 39.457132] == 964 Write Reg[0x4C] = 0x24 [ 39.457625] == 964 Write Reg[0x6E] = 0x88 [ 39.458117] == 964 Write Reg[0x6F] = 0x9A [ 39.458608] == 964 Write Reg[0x4C] = 0x38 [ 39.459100] == 964 Write Reg[0x6E] = 0x88 [ 39.459593] == 964 Write Reg[0x6F] = 0x9A [ 39.460085] == 964 Write Reg[0x10] = 0x91 [ 39.460577] == 964 Write Reg[0x19] = 0x01 [ 39.461068] == 964 Write Reg[0x1A] = 0x4D [ 39.461558] == 964 Write Reg[0x1B] = 0x0B [ 39.462050] == 964 Write Reg[0x1C] = 0xB7 [ 39.462544] == 964 Write Reg[0x18] = 0x01 [ 39.464505] == 964 Write Reg[0x21] = 0x3C init_initb RX0 [ 39.465028] == 964 Write Reg[0x4C] = 0x01 [ 39.484305] == 964 Write Reg[0x36] = 0x10 [ 39.504300] == 964 Write Reg[0xD8] = 0x07 [ 39.524299] == 964 Write Reg[0xD9] = 0x17 [ 39.544316] == 964 Write Reg[0x37] = 0x10 [ 39.724743] == 964 Write Reg[0x23] = 0xBF init_initb RX1 [ 39.747157] == 964 Write Reg[0x4C] = 0x12 [ 39.764097] == 964 Write Reg[0x36] = 0x10 [ 39.784115] == 964 Write Reg[0xD8] = 0x07 [ 39.804104] == 964 Write Reg[0xD9] = 0x17 [ 39.824427] == 964 Write Reg[0x37] = 0x10 [ 39.844292] == 964 Write Reg[0x37] = 0x10 [ 39.864283] == 964 Write Reg[0x23] = 0xBF init_initb RX2 [ 39.887644] == 964 Write Reg[0x4C] = 0x24 [ 39.904274] == 964 Write Reg[0x36] = 0x10 [ 39.924253] == 964 Write Reg[0xD8] = 0x07 [ 39.988816] == 964 Write Reg[0xD9] = 0x17 [ 40.004265] == 964 Write Reg[0x37] = 0x10 [ 40.024247] == 964 Write Reg[0x37] = 0x10 [ 40.044249] == 964 Write Reg[0x37] = 0x10 [ 40.064260] == 964 Write Reg[0x23] = 0xBF init_initb RX3 [ 40.087651] == 964 Write Reg[0x4C] = 0x38 [ 40.104253] == 964 Write Reg[0x36] = 0x10 [ 40.124246] == 964 Write Reg[0xD8] = 0x07 [ 40.144249] == 964 Write Reg[0xD9] = 0x17 [ 40.164250] == 964 Write Reg[0x37] = 0x10 [ 40.184246] == 964 Write Reg[0x37] = 0x10 [ 40.248799] == 964 Write Reg[0x37] = 0x10 [ 40.264285] == 964 Write Reg[0x23] = 0xBF [ 40.287137] ds901b964: num = 1, mask = 0x1. [ 40.287144] >>> Initialize done <<< [ 40.287334] get lanes = 3 [ 40.287343] in ds901b964_kthread() start [ 40.287380] mxc_mipi_csi2 21dc000.mipi_csi: mipi_csi2_reset: value = 0x14, bps = 800 Mbps. [ 40.453048] in ds901b964_work_func() ti964_intb_isEnable=false [ 40.508167] == 964 read Reg[0x24] = 0x91 [ 40.508681] == 964 Write Reg[0x4C] = 0x01 [ 40.509330] == 964 read Reg[0xDB] = 0x70 [ 40.509979] == 964 read Reg[0xDA] = 0x00 [ 40.510628] == 964 read Reg[0x4D] = 0x03 [ 40.511274] == 964 read Reg[0x4E] = 0x55 [ 40.511770] == 964 Write Reg[0x4C] = 0x12 [ 40.512414] == 964 read Reg[0xDB] = 0x00 [ 40.513770] == 964 read Reg[0xDA] = 0x00 [ 40.514455] == 964 read Reg[0x4D] = 0x40 [ 40.515128] == 964 read Reg[0x4E] = 0x02 [ 40.515642] == 964 Write Reg[0x4C] = 0x24 [ 40.516313] == 964 read Reg[0xDB] = 0x00 [ 40.516987] == 964 read Reg[0xDA] = 0x00 [ 40.517726] == 964 read Reg[0x4D] = 0x80 [ 40.518398] == 964 read Reg[0x4E] = 0x02 [ 40.518912] == 964 Write Reg[0x4C] = 0x38 [ 40.519583] == 964 read Reg[0xDB] = 0x00 [ 40.520256] == 964 read Reg[0xDA] = 0x00 [ 40.520926] == 964 read Reg[0x4D] = 0xC0 [ 40.521598] == 964 read Reg[0x4E] = 0x02 [ 40.521612] ===>in showTI964Status(): STS=0x91 [ 40.521630] LO[0]=0x70 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x55 [ 40.521646] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.521660] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.521674] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.521684] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.521693] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.521702] in showTI964Status() # IS_RX0 DETECTED [ 40.521711] in showTI964Status() 0: # IS_LINE_LEN_CHG INTERRUPT DETECTED [ 40.521721] in showTI964Status() 0: # IS_LINE_CNT_CHG DETECTED [ 40.521730] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.521739] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.521748] in showTI964Status() 0: # PORT_PASS=1 [ 40.521756] in showTI964Status() 0: # LOCK_STS=1 [ 40.521765] in showTI964Status() 0: # LINE_LEN_CHG [ 40.521775] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.521784] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.521793] in showTI964Status() 0: # LINE_CNT_CHG DETECTED [ 40.521802] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.521811] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.521820] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.521829] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.521839] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.521848] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.521862] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 40.522053] ===>in ds901b964_irq_handler() IRQ handler [ 40.522765] == 964 read Reg[0x24] = 0x91 [ 40.523375] == 964 Write Reg[0x4C] = 0x01 [ 40.524055] == 964 read Reg[0xDB] = 0x10 [ 40.524734] == 964 read Reg[0xDA] = 0x00 [ 40.525408] == 964 read Reg[0x4D] = 0x03 [ 40.526081] == 964 read Reg[0x4E] = 0x14 [ 40.526594] == 964 Write Reg[0x4C] = 0x12 [ 40.527268] == 964 read Reg[0xDB] = 0x00 [ 40.527976] == 964 read Reg[0xDA] = 0x00 [ 40.528624] == 964 read Reg[0x4D] = 0x40 [ 40.529269] == 964 read Reg[0x4E] = 0x02 [ 40.529762] == 964 Write Reg[0x4C] = 0x24 [ 40.530406] == 964 read Reg[0xDB] = 0x00 [ 40.531050] == 964 read Reg[0xDA] = 0x00 [ 40.531697] == 964 read Reg[0x4D] = 0x80 [ 40.532341] == 964 read Reg[0x4E] = 0x02 [ 40.532835] == 964 Write Reg[0x4C] = 0x38 [ 40.534336] == 964 read Reg[0xDB] = 0x00 [ 40.535015] == 964 read Reg[0xDA] = 0x00 [ 40.535695] == 964 read Reg[0x4D] = 0xC0 [ 40.536368] == 964 read Reg[0x4E] = 0x02 [ 40.536383] ===>in showTI964Status(): STS=0x91 [ 40.536401] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 40.536416] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.536431] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.536445] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.536455] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.536464] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.536472] in showTI964Status() # IS_RX0 DETECTED [ 40.536481] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.536491] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.536499] in showTI964Status() 0: # PORT_PASS=1 [ 40.536509] in showTI964Status() 0: # LOCK_STS=1 [ 40.536517] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.536526] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.536535] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.536544] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.536553] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.536562] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.536571] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.536580] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.536594] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 40.561983] ===>in ds901b964_irq_handler() IRQ handler [ 40.562694] == 964 read Reg[0x24] = 0x91 [ 40.563291] == 964 Write Reg[0x4C] = 0x01 [ 40.563994] == 964 read Reg[0xDB] = 0x10 [ 40.564668] == 964 read Reg[0xDA] = 0x00 [ 40.565314] == 964 read Reg[0x4D] = 0x03 [ 40.565961] == 964 read Reg[0x4E] = 0x14 [ 40.566454] == 964 Write Reg[0x4C] = 0x12 [ 40.567100] == 964 read Reg[0xDB] = 0x00 [ 40.567744] == 964 read Reg[0xDA] = 0x00 [ 40.568407] == 964 read Reg[0x4D] = 0x40 [ 40.569055] == 964 read Reg[0x4E] = 0x02 [ 40.569548] == 964 Write Reg[0x4C] = 0x24 [ 40.570199] == 964 read Reg[0xDB] = 0x00 [ 40.570846] == 964 read Reg[0xDA] = 0x00 [ 40.571489] == 964 read Reg[0x4D] = 0x80 [ 40.572137] == 964 read Reg[0x4E] = 0x02 [ 40.572628] == 964 Write Reg[0x4C] = 0x38 [ 40.573294] == 964 read Reg[0xDB] = 0x00 [ 40.573964] == 964 read Reg[0xDA] = 0x00 [ 40.574633] == 964 read Reg[0x4D] = 0xC0 [ 40.575299] == 964 read Reg[0x4E] = 0x02 [ 40.575313] ===>in showTI964Status(): STS=0x91 [ 40.575331] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 40.575346] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.575361] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.575376] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.575385] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.575394] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.575403] in showTI964Status() # IS_RX0 DETECTED [ 40.575412] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.575421] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.575430] in showTI964Status() 0: # PORT_PASS=1 [ 40.575438] in showTI964Status() 0: # LOCK_STS=1 [ 40.575447] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.575456] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.575465] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.575474] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.575483] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.575491] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.575501] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.575509] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.575523] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 40.601913] ===>in ds901b964_irq_handler() IRQ handler [ 40.602622] == 964 read Reg[0x24] = 0x91 [ 40.603201] == 964 Write Reg[0x4C] = 0x01 [ 40.603899] == 964 read Reg[0xDB] = 0x10 [ 40.604570] == 964 read Reg[0xDA] = 0x00 [ 40.605236] == 964 read Reg[0x4D] = 0x03 [ 40.605897] == 964 read Reg[0x4E] = 0x14 [ 40.606410] == 964 Write Reg[0x4C] = 0x12 [ 40.607074] == 964 read Reg[0xDB] = 0x00 [ 40.607739] == 964 read Reg[0xDA] = 0x00 [ 40.608403] == 964 read Reg[0x4D] = 0x40 [ 40.609131] == 964 read Reg[0x4E] = 0x02 [ 40.609639] == 964 Write Reg[0x4C] = 0x24 [ 40.610303] == 964 read Reg[0xDB] = 0x00 [ 40.610968] == 964 read Reg[0xDA] = 0x00 [ 40.611634] == 964 read Reg[0x4D] = 0x80 [ 40.612296] == 964 read Reg[0x4E] = 0x02 [ 40.612805] == 964 Write Reg[0x4C] = 0x38 [ 40.613509] == 964 read Reg[0xDB] = 0x00 [ 40.614165] == 964 read Reg[0xDA] = 0x00 [ 40.614820] == 964 read Reg[0x4D] = 0xC0 [ 40.615469] == 964 read Reg[0x4E] = 0x02 [ 40.615482] ===>in showTI964Status(): STS=0x91 [ 40.615500] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 40.615516] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.615531] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.615546] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.615555] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.615563] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.615572] in showTI964Status() # IS_RX0 DETECTED [ 40.615581] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.615590] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.615599] in showTI964Status() 0: # PORT_PASS=1 [ 40.615607] in showTI964Status() 0: # LOCK_STS=1 [ 40.615616] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.615625] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.615633] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.615642] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.615651] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.615660] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.615669] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.615678] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.615691] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 40.641843] ===>in ds901b964_irq_handler() IRQ handler [ 40.642551] == 964 read Reg[0x24] = 0x91 [ 40.643057] == 964 Write Reg[0x4C] = 0x01 [ 40.643805] == 964 read Reg[0xDB] = 0x10 [ 40.644475] == 964 read Reg[0xDA] = 0x00 [ 40.645141] == 964 read Reg[0x4D] = 0x03 [ 40.645807] == 964 read Reg[0x4E] = 0x14 [ 40.646314] == 964 Write Reg[0x4C] = 0x12 [ 40.646979] == 964 read Reg[0xDB] = 0x00 [ 40.647644] == 964 read Reg[0xDA] = 0x00 [ 40.648307] == 964 read Reg[0x4D] = 0x40 [ 40.648972] == 964 read Reg[0x4E] = 0x02 [ 40.649546] == 964 Write Reg[0x4C] = 0x24 [ 40.650216] == 964 read Reg[0xDB] = 0x00 [ 40.650879] == 964 read Reg[0xDA] = 0x00 [ 40.651544] == 964 read Reg[0x4D] = 0x80 [ 40.652208] == 964 read Reg[0x4E] = 0x02 [ 40.652718] == 964 Write Reg[0x4C] = 0x38 [ 40.653402] == 964 read Reg[0xDB] = 0x00 [ 40.654074] == 964 read Reg[0xDA] = 0x00 [ 40.654739] == 964 read Reg[0x4D] = 0xC0 [ 40.655404] == 964 read Reg[0x4E] = 0x02 [ 40.655418] ===>in showTI964Status(): STS=0x91 [ 40.655435] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 40.655450] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.655466] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.655480] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.655489] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.655499] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.655507] in showTI964Status() # IS_RX0 DETECTED [ 40.655516] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.655525] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.655534] in showTI964Status() 0: # PORT_PASS=1 [ 40.655543] in showTI964Status() 0: # LOCK_STS=1 [ 40.655551] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.655560] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.655569] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.655577] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.655586] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.655595] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.655604] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.655612] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.655625] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 40.681774] ===>in ds901b964_irq_handler() IRQ handler [ 40.682479] == 964 read Reg[0x24] = 0x91 [ 40.683077] == 964 Write Reg[0x4C] = 0x01 [ 40.683781] == 964 read Reg[0xDB] = 0x10 [ 40.684457] == 964 read Reg[0xDA] = 0x00 [ 40.685131] == 964 read Reg[0x4D] = 0x03 [ 40.685805] == 964 read Reg[0x4E] = 0x14 [ 40.686317] == 964 Write Reg[0x4C] = 0x12 [ 40.686989] == 964 read Reg[0xDB] = 0x00 [ 40.687661] == 964 read Reg[0xDA] = 0x00 [ 40.688333] == 964 read Reg[0x4D] = 0x40 [ 40.689010] == 964 read Reg[0x4E] = 0x02 [ 40.689582] == 964 Write Reg[0x4C] = 0x24 [ 40.690257] == 964 read Reg[0xDB] = 0x00 [ 40.690931] == 964 read Reg[0xDA] = 0x00 [ 40.691605] == 964 read Reg[0x4D] = 0x80 [ 40.692276] == 964 read Reg[0x4E] = 0x02 [ 40.692789] == 964 Write Reg[0x4C] = 0x38 [ 40.693509] == 964 read Reg[0xDB] = 0x00 [ 40.694181] == 964 read Reg[0xDA] = 0x00 [ 40.694858] == 964 read Reg[0x4D] = 0xC0 [ 40.695531] == 964 read Reg[0x4E] = 0x02 [ 40.695544] ===>in showTI964Status(): STS=0x91 [ 40.695562] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 40.695577] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.695592] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.695607] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.695616] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.695625] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.695633] in showTI964Status() # IS_RX0 DETECTED [ 40.695642] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.695651] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.695660] in showTI964Status() 0: # PORT_PASS=1 [ 40.695669] in showTI964Status() 0: # LOCK_STS=1 [ 40.695677] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.695686] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.695695] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.695704] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.695713] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.695722] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.695731] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.695740] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.695753] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 40.721705] ===>in ds901b964_irq_handler() IRQ handler [ 40.722409] == 964 read Reg[0x24] = 0x91 [ 40.722915] == 964 Write Reg[0x4C] = 0x01 [ 40.723698] == 964 read Reg[0xDB] = 0x10 [ 40.724375] == 964 read Reg[0xDA] = 0x00 [ 40.725052] == 964 read Reg[0x4D] = 0x03 [ 40.725725] == 964 read Reg[0x4E] = 0x14 [ 40.726236] == 964 Write Reg[0x4C] = 0x12 [ 40.726909] == 964 read Reg[0xDB] = 0x00 [ 40.727582] == 964 read Reg[0xDA] = 0x00 [ 40.728253] == 964 read Reg[0x4D] = 0x40 [ 40.728926] == 964 read Reg[0x4E] = 0x02 [ 40.729438] == 964 Write Reg[0x4C] = 0x24 [ 40.730172] == 964 read Reg[0xDB] = 0x00 [ 40.730844] == 964 read Reg[0xDA] = 0x00 [ 40.731517] == 964 read Reg[0x4D] = 0x80 [ 40.732189] == 964 read Reg[0x4E] = 0x02 [ 40.732702] == 964 Write Reg[0x4C] = 0x38 [ 40.733376] == 964 read Reg[0xDB] = 0x00 [ 40.734046] == 964 read Reg[0xDA] = 0x00 [ 40.734717] == 964 read Reg[0x4D] = 0xC0 [ 40.735392] == 964 read Reg[0x4E] = 0x02 [ 40.735407] ===>in showTI964Status(): STS=0x91 [ 40.735424] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 40.735439] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.735453] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.735468] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.735477] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.735486] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.735494] in showTI964Status() # IS_RX0 DETECTED [ 40.735503] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.735512] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.735521] in showTI964Status() 0: # PORT_PASS=1 [ 40.735529] in showTI964Status() 0: # LOCK_STS=1 [ 40.735537] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.735546] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.735567] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.735585] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.735604] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.735623] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.735636] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.735645] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.735658] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 40.761635] ===>in ds901b964_irq_handler() IRQ handler [ 40.762344] == 964 read Reg[0x24] = 0x91 [ 40.762850] == 964 Write Reg[0x4C] = 0x01 [ 40.763576] == 964 read Reg[0xDB] = 0x10 [ 40.764275] == 964 read Reg[0xDA] = 0x00 [ 40.764949] == 964 read Reg[0x4D] = 0x03 [ 40.765624] == 964 read Reg[0x4E] = 0x14 [ 40.766136] == 964 Write Reg[0x4C] = 0x12 [ 40.766808] == 964 read Reg[0xDB] = 0x00 [ 40.767478] == 964 read Reg[0xDA] = 0x00 [ 40.768149] == 964 read Reg[0x4D] = 0x40 [ 40.768821] == 964 read Reg[0x4E] = 0x02 [ 40.769335] == 964 Write Reg[0x4C] = 0x24 [ 40.770006] == 964 read Reg[0xDB] = 0x00 [ 40.770676] == 964 read Reg[0xDA] = 0x00 [ 40.771330] == 964 read Reg[0x4D] = 0x80 [ 40.771986] == 964 read Reg[0x4E] = 0x02 [ 40.772498] == 964 Write Reg[0x4C] = 0x38 [ 40.773217] == 964 read Reg[0xDB] = 0x00 [ 40.773890] == 964 read Reg[0xDA] = 0x00 [ 40.774562] == 964 read Reg[0x4D] = 0xC0 [ 40.775234] == 964 read Reg[0x4E] = 0x02 [ 40.775248] ===>in showTI964Status(): STS=0x91 [ 40.775265] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 40.775281] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.775295] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.775309] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.775318] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.775327] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.775336] in showTI964Status() # IS_RX0 DETECTED [ 40.775345] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.775355] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.775363] in showTI964Status() 0: # PORT_PASS=1 [ 40.775371] in showTI964Status() 0: # LOCK_STS=1 [ 40.775380] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.775388] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.775397] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.775406] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.775414] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.775423] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.775431] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.775439] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.775452] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 40.801567] ===>in ds901b964_irq_handler() IRQ handler [ 40.802273] == 964 read Reg[0x24] = 0x91 [ 40.802783] == 964 Write Reg[0x4C] = 0x01 [ 40.803520] == 964 read Reg[0xDB] = 0x10 [ 40.804200] == 964 read Reg[0xDA] = 0x00 [ 40.804874] == 964 read Reg[0x4D] = 0x03 [ 40.805544] == 964 read Reg[0x4E] = 0x14 [ 40.806058] == 964 Write Reg[0x4C] = 0x12 [ 40.806735] == 964 read Reg[0xDB] = 0x00 [ 40.807408] == 964 read Reg[0xDA] = 0x00 [ 40.808079] == 964 read Reg[0x4D] = 0x40 [ 40.808749] == 964 read Reg[0x4E] = 0x02 [ 40.809263] == 964 Write Reg[0x4C] = 0x24 [ 40.809933] == 964 read Reg[0xDB] = 0x00 [ 40.810603] == 964 read Reg[0xDA] = 0x00 [ 40.811272] == 964 read Reg[0x4D] = 0x80 [ 40.811922] == 964 read Reg[0x4E] = 0x02 [ 40.812437] == 964 Write Reg[0x4C] = 0x38 [ 40.813115] == 964 read Reg[0xDB] = 0x00 [ 40.813812] == 964 read Reg[0xDA] = 0x00 [ 40.814508] == 964 read Reg[0x4D] = 0xC0 [ 40.815203] == 964 read Reg[0x4E] = 0x02 [ 40.815216] ===>in showTI964Status(): STS=0x91 [ 40.815233] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 40.815248] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.815262] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.815276] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.815285] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.815294] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.815302] in showTI964Status() # IS_RX0 DETECTED [ 40.815311] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.815320] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.815328] in showTI964Status() 0: # PORT_PASS=1 [ 40.815336] in showTI964Status() 0: # LOCK_STS=1 [ 40.815345] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.815353] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.815362] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.815371] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.815379] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.815396] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.815414] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.815431] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.815452] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 40.841498] ===>in ds901b964_irq_handler() IRQ handler [ 40.842262] == 964 read Reg[0x24] = 0x91 [ 40.842773] == 964 Write Reg[0x4C] = 0x01 [ 40.843517] == 964 read Reg[0xDB] = 0x10 [ 40.844186] == 964 read Reg[0xDA] = 0x00 [ 40.844853] == 964 read Reg[0x4D] = 0x03 [ 40.845520] == 964 read Reg[0x4E] = 0x14 [ 40.846026] == 964 Write Reg[0x4C] = 0x12 [ 40.846692] == 964 read Reg[0xDB] = 0x00 [ 40.847355] == 964 read Reg[0xDA] = 0x00 [ 40.848020] == 964 read Reg[0x4D] = 0x40 [ 40.848684] == 964 read Reg[0x4E] = 0x02 [ 40.849190] == 964 Write Reg[0x4C] = 0x24 [ 40.849855] == 964 read Reg[0xDB] = 0x00 [ 40.850520] == 964 read Reg[0xDA] = 0x00 [ 40.851182] == 964 read Reg[0x4D] = 0x80 [ 40.851844] == 964 read Reg[0x4E] = 0x02 [ 40.852348] == 964 Write Reg[0x4C] = 0x38 [ 40.853081] == 964 read Reg[0xDB] = 0x00 [ 40.853789] == 964 read Reg[0xDA] = 0x00 [ 40.854484] == 964 read Reg[0x4D] = 0xC0 [ 40.855178] == 964 read Reg[0x4E] = 0x02 [ 40.855192] ===>in showTI964Status(): STS=0x91 [ 40.855209] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 40.855224] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.855238] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.855253] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.855262] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.855270] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.855278] in showTI964Status() # IS_RX0 DETECTED [ 40.855288] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.855309] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.855326] in showTI964Status() 0: # PORT_PASS=1 [ 40.855343] in showTI964Status() 0: # LOCK_STS=1 [ 40.855358] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.855367] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.855376] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.855384] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.855393] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.855402] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.855410] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.855419] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.855432] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 40.881429] ===>in ds901b964_irq_handler() IRQ handler [ 40.882200] == 964 read Reg[0x24] = 0x91 [ 40.882709] == 964 Write Reg[0x4C] = 0x01 [ 40.883360] == 964 read Reg[0xDB] = 0x10 [ 40.884059] == 964 read Reg[0xDA] = 0x00 [ 40.884725] == 964 read Reg[0x4D] = 0x03 [ 40.885391] == 964 read Reg[0x4E] = 0x14 [ 40.885898] == 964 Write Reg[0x4C] = 0x12 [ 40.886563] == 964 read Reg[0xDB] = 0x00 [ 40.887226] == 964 read Reg[0xDA] = 0x00 [ 40.887890] == 964 read Reg[0x4D] = 0x40 [ 40.888555] == 964 read Reg[0x4E] = 0x02 [ 40.889063] == 964 Write Reg[0x4C] = 0x24 [ 40.889731] == 964 read Reg[0xDB] = 0x00 [ 40.890395] == 964 read Reg[0xDA] = 0x00 [ 40.891058] == 964 read Reg[0x4D] = 0x80 [ 40.891721] == 964 read Reg[0x4E] = 0x02 [ 40.892238] == 964 Write Reg[0x4C] = 0x38 [ 40.892910] == 964 read Reg[0xDB] = 0x00 [ 40.893655] == 964 read Reg[0xDA] = 0x00 [ 40.894331] == 964 read Reg[0x4D] = 0xC0 [ 40.895002] == 964 read Reg[0x4E] = 0x02 [ 40.895015] ===>in showTI964Status(): STS=0x91 [ 40.895033] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 40.895048] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.895063] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.895076] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.895085] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.895094] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.895102] in showTI964Status() # IS_RX0 DETECTED [ 40.895111] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.895128] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.895148] in showTI964Status() 0: # PORT_PASS=1 [ 40.895165] in showTI964Status() 0: # LOCK_STS=1 [ 40.895182] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.895191] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.895200] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.895208] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.895217] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.895225] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.895234] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.895243] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.895256] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 40.921359] ===>in ds901b964_irq_handler() IRQ handler [ 40.922068] == 964 read Reg[0x24] = 0x91 [ 40.922586] == 964 Write Reg[0x4C] = 0x01 [ 40.923263] == 964 read Reg[0xDB] = 0x10 [ 40.923939] == 964 read Reg[0xDA] = 0x00 [ 40.924607] == 964 read Reg[0x4D] = 0x03 [ 40.925275] == 964 read Reg[0x4E] = 0x14 [ 40.925783] == 964 Write Reg[0x4C] = 0x12 [ 40.926447] == 964 read Reg[0xDB] = 0x00 [ 40.927111] == 964 read Reg[0xDA] = 0x00 [ 40.927775] == 964 read Reg[0x4D] = 0x40 [ 40.928439] == 964 read Reg[0x4E] = 0x02 [ 40.928948] == 964 Write Reg[0x4C] = 0x24 [ 40.929613] == 964 read Reg[0xDB] = 0x00 [ 40.930278] == 964 read Reg[0xDA] = 0x00 [ 40.930944] == 964 read Reg[0x4D] = 0x80 [ 40.931608] == 964 read Reg[0x4E] = 0x02 [ 40.932114] == 964 Write Reg[0x4C] = 0x38 [ 40.932775] == 964 read Reg[0xDB] = 0x00 [ 40.933538] == 964 read Reg[0xDA] = 0x00 [ 40.934243] == 964 read Reg[0x4D] = 0xC0 [ 40.934948] == 964 read Reg[0x4E] = 0x02 [ 40.934962] ===>in showTI964Status(): STS=0x91 [ 40.934979] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 40.934995] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.935009] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.935024] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.935034] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.935043] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.935052] in showTI964Status() # IS_RX0 DETECTED [ 40.935061] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.935070] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.935078] in showTI964Status() 0: # PORT_PASS=1 [ 40.935087] in showTI964Status() 0: # LOCK_STS=1 [ 40.935095] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.935104] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.935112] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.935121] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.935137] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.935157] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.935174] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.935191] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.935215] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 40.961292] ===>in ds901b964_irq_handler() IRQ handler [ 40.962055] == 964 read Reg[0x24] = 0x91 [ 40.962569] == 964 Write Reg[0x4C] = 0x01 [ 40.963245] == 964 read Reg[0xDB] = 0x10 [ 40.963918] == 964 read Reg[0xDA] = 0x00 [ 40.964585] == 964 read Reg[0x4D] = 0x03 [ 40.965251] == 964 read Reg[0x4E] = 0x14 [ 40.965759] == 964 Write Reg[0x4C] = 0x12 [ 40.966424] == 964 read Reg[0xDB] = 0x00 [ 40.967088] == 964 read Reg[0xDA] = 0x00 [ 40.967752] == 964 read Reg[0x4D] = 0x40 [ 40.968417] == 964 read Reg[0x4E] = 0x02 [ 40.968924] == 964 Write Reg[0x4C] = 0x24 [ 40.969589] == 964 read Reg[0xDB] = 0x00 [ 40.970253] == 964 read Reg[0xDA] = 0x00 [ 40.970917] == 964 read Reg[0x4D] = 0x80 [ 40.971586] == 964 read Reg[0x4E] = 0x02 [ 40.972093] == 964 Write Reg[0x4C] = 0x38 [ 40.972759] == 964 read Reg[0xDB] = 0x00 [ 40.973530] == 964 read Reg[0xDA] = 0x00 [ 40.974237] == 964 read Reg[0x4D] = 0xC0 [ 40.974944] == 964 read Reg[0x4E] = 0x02 [ 40.974957] ===>in showTI964Status(): STS=0x91 [ 40.974974] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 40.974990] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 40.975004] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 40.975017] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 40.975027] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 40.975035] in showTI964Status() # IS_CSI_TX0 DETECTED [ 40.975044] in showTI964Status() # IS_RX0 DETECTED [ 40.975053] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 40.975062] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 40.975070] in showTI964Status() 0: # PORT_PASS=1 [ 40.975079] in showTI964Status() 0: # LOCK_STS=1 [ 40.975089] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 40.975097] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 40.975106] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 40.975115] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 40.975124] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 40.975133] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 40.975153] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 40.975171] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 40.975192] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 41.001220] ===>in ds901b964_irq_handler() IRQ handler [ 41.001985] == 964 read Reg[0x24] = 0x91 [ 41.002498] == 964 Write Reg[0x4C] = 0x01 [ 41.003212] == 964 read Reg[0xDB] = 0x10 [ 41.003888] == 964 read Reg[0xDA] = 0x00 [ 41.004557] == 964 read Reg[0x4D] = 0x03 [ 41.005222] == 964 read Reg[0x4E] = 0x14 [ 41.005730] == 964 Write Reg[0x4C] = 0x12 [ 41.006394] == 964 read Reg[0xDB] = 0x00 [ 41.010117] == 964 read Reg[0xDA] = 0x00 [ 41.012924] == 964 read Reg[0x4D] = 0x40 [ 41.013692] == 964 read Reg[0x4E] = 0x02 [ 41.014198] == 964 Write Reg[0x4C] = 0x24 [ 41.014844] == 964 read Reg[0xDB] = 0x00 [ 41.015490] == 964 read Reg[0xDA] = 0x00 [ 41.016133] == 964 read Reg[0x4D] = 0x80 [ 41.016778] == 964 read Reg[0x4E] = 0x02 [ 41.017271] == 964 Write Reg[0x4C] = 0x38 [ 41.017916] == 964 read Reg[0xDB] = 0x00 [ 41.018760] == 964 read Reg[0xDA] = 0x00 [ 41.024793] == 964 read Reg[0x4D] = 0xC0 [ 41.025465] == 964 read Reg[0x4E] = 0x02 [ 41.025481] ===>in showTI964Status(): STS=0x91 [ 41.025499] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 41.025519] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 41.025535] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 41.025549] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 41.025564] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 41.025573] in showTI964Status() # IS_CSI_TX0 DETECTED [ 41.025582] in showTI964Status() # IS_RX0 DETECTED [ 41.025592] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 41.025602] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 41.025617] in showTI964Status() 0: # PORT_PASS=1 [ 41.025626] in showTI964Status() 0: # LOCK_STS=1 [ 41.025635] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 41.025644] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 41.025653] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 41.025662] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 41.025671] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 41.025684] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 41.025693] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 41.025702] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 41.025717] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00 [ 41.041155] ===>in ds901b964_irq_handler() IRQ handler [ 41.041886] == 964 read Reg[0x24] = 0x91 [ 41.042405] == 964 Write Reg[0x4C] = 0x01 [ 41.043442] == 964 read Reg[0xDB] = 0x10 [ 41.044126] == 964 read Reg[0xDA] = 0x00 [ 41.044803] == 964 read Reg[0x4D] = 0x03 [ 41.045483] == 964 read Reg[0x4E] = 0x14 [ 41.046004] == 964 Write Reg[0x4C] = 0x12 [ 41.046676] == 964 read Reg[0xDB] = 0x00 [ 41.047350] == 964 read Reg[0xDA] = 0x00 [ 41.048019] == 964 read Reg[0x4D] = 0x40 [ 41.048689] == 964 read Reg[0x4E] = 0x02 [ 41.049205] == 964 Write Reg[0x4C] = 0x24 [ 41.049879] == 964 read Reg[0xDB] = 0x00 [ 41.050555] == 964 read Reg[0xDA] = 0x00 [ 41.051223] == 964 read Reg[0x4D] = 0x80 [ 41.051895] == 964 read Reg[0x4E] = 0x02 [ 41.052402] == 964 Write Reg[0x4C] = 0x38 [ 41.054786] == 964 read Reg[0xDB] = 0x00 [ 41.055382] == 964 read Reg[0xDA] = 0x00 [ 41.055967] == 964 read Reg[0x4D] = 0xC0 [ 41.056554] == 964 read Reg[0x4E] = 0x02 [ 41.056563] ===>in showTI964Status(): STS=0x91 [ 41.056570] LO[0]=0x10 HI[0]=0x00 ST1[0]=0x03 ST2[0]=0x14 [ 41.056576] LO[1]=0x00 HI[1]=0x00 ST1[1]=0x40 ST2[1]=0x02 [ 41.056585] LO[2]=0x00 HI[2]=0x00 ST1[2]=0x80 ST2[2]=0x02 [ 41.056591] LO[3]=0x00 HI[3]=0x00 ST1[3]=0xc0 ST2[3]=0x02 [ 41.056594] in showTI964Status() # GLOBAL INTERRUPT DETECTED [ 41.056598] in showTI964Status() # IS_CSI_TX0 DETECTED [ 41.056602] in showTI964Status() # IS_RX0 DETECTED [ 41.056608] in showTI964Status() 0: # IS_BUFFER_ERR DETECTED [ 41.056613] in showTI964Status() 0: # RX_PORT_NUM = RX0 [ 41.056616] in showTI964Status() 0: # PORT_PASS=1 [ 41.056620] in showTI964Status() 0: # LOCK_STS=1 [ 41.056625] in showTI964Status() 0: # BUFFER_ERROR DETECTED [ 41.056631] in showTI964Status() 0: # FREQ_STABLE DETECTED [ 41.056634] in showTI964Status() 1: # RX_PORT_NUM = RX1 [ 41.056638] in showTI964Status() 1: # NO_FPD3_CLK DETECTED [ 41.056642] in showTI964Status() 2: # RX_PORT_NUM = RX2 [ 41.056646] in showTI964Status() 2: # NO_FPD3_CLK DETECTED [ 41.056652] in showTI964Status() 3: # RX_PORT_NUM = RX3 [ 41.056655] in showTI964Status() 3: # NO_FPD3_CLK DETECTED [ 41.056661] ds901b964_work_func old_mask=0x01 new_mask=0x01 sub_mask=0x00 add_mask=0x00
Hi Xiao,
In your code I don't see the FrameSync signal being outputted on the serializer side. Is that intentional? Do you only intend the output the FrameSync to deserializer GPIO0?
What's the duty cycle of the FrameSync you intend to use? You are using back channel 50MHz right?
Just wanted to make sure these registers are programmed correctly:
[ 39.460577] == 964 Write Reg[0x19] = 0x01
[ 39.461068] == 964 Write Reg[0x1A] = 0x4D
[ 39.461558] == 964 Write Reg[0x1B] = 0x0B
[ 39.462050] == 964 Write Reg[0x1C] = 0xB7
For the default BC Freq of 50MHz, Frame period = 600 ns --> 27778 counts:
For a 50% duty cycle, set high time & low time to 13889 -> (0x3641)
Could you try this and see if your issue disappears?
Best,
Jiashow
Hello Jiashow
The 964 back channel freq default is 2.5Mhz. 964 used refclk is 24.96Mhz, so the back channel should be 2.496Mhz. the serializer used 4 933. and the frame is 25Hz. So based on this , how to setup the four register?
Hi Xiao,
Based on the back channel, the frame period is ~12us. If the FrameSync frequency is 25Hz, then the total count is (1 sec / 25Hz) / 12 us = 3334
For FrameSync of 25Hz with duty cycle 50%. Try setting reg 0x19 - 0x1C to the following:
FS_HIGH_TIME_1: 0x06
FS_HIGH_TIME_0: 0x83
FS_LOW_TIME_1: 0x06
FS_LOW_TIME_0: 0x83
For FrameSync of 25Hz with duty cycle 10%. Try setting reg 0x19 - 0x1C to the following:
FS_HIGH_TIME_1: 0x01
FS_HIGH_TIME_0: 0x4D
FS_LOW_TIME_1: 0x0B
FS_LOW_TIME_0: 0xB9
Best,
Jiashow
