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SN65HVD70: The level of input

Liu Yang
Expert 5945 points
Part Number: SN65HVD70

Hi Team,

Please help me answer the follow question, thank you so much.

SN65HVD70 IC is used in RS485 secification. The input A and the output Y are connected.

When the DE is set to "L" then the output is high impedance, the level of the date+ line(the input A and the output Y)  becomes about 1V. 

What is the reason? Does the input A has an internal pullup resistor?

BR

Tom.Liu

  • 0
    TI__Guru 62920 points
    Hi Tom,

    Yes, the voltage observed during the idle state is due to some internal resistances in the receiver input circuit. You can see an equivalent input circuit diagram in Figure 28 of the datasheet. There are both pull-up and pull-down resistances, and so the measured voltages should be somewhere between GND and VCC. Note that these are fairly high resistances, and so this bias voltage would be easily overdriven whenever a driver circuit is active.

    Please let us know if you have any further questions.

    Regards,
    Max
  • 0 in reply to Miguel Robertson
    TI__Expert 5945 points
    Hi Max,

    I'm sorry for the late reply. Actually I have a further question below.
    I understood that the input resistance of the receiver section determines the voltage of the +data line. Our measured value is about +1V. Is intentional or accidental biasing to the +side? The IC which does not have the failsafe function put the pull-up resistor in the place of the +data line on the external, does it related to this?

    BR
    Tom.Liu
  • 0 in reply to Liu Yang
    TI__Guru 62920 points
    Hi Tom,

    The ~1-V level is intentional and is set by the ratio of the internal pull-up and pull-down resistances in the device. Note that these resistances are actually not used for failsafe biasing, though. Instead, they are used to scale the input voltages (which can range from -7 V to +12 V per the RS-485 standard's common mode range) into a voltage range that allows for better operation of the receiver circuitry (i.e., a voltage range between the device's ground and VCC levels). The failsafe function is actually implemented via an offset voltage in the input comparator.

    Some RS-485 transceivers use different pull-up/pull-down ratios on the A and B signal lines, and so in these cases the resistances also provide a failsafe biasing effect. In either case, external pull-up and pull-down resistances can be used as well to impose a greater failsafe bias. (Most RS-485 transceivers will have a high input impedance in order to be able to support a large number of nodes on a network, and so even larger external resistance values can be effective in creating an additional input bias offset voltage.)

    Here's a blog on RS-485 receivers that may be useful as a reference to you:

    e2e.ti.com/.../rs-485-basics-the-rs-485-receiver

    Please let us know if you have any further questions.

    Regards,
    Max