Hi,
We are working on a radio product which works in 125MHz band. and hence we have a limitation in our design on usage of 25MHz,
We are planning to operate DP83822I PHY in RMII slave mode. The PHY and MAC will be fed from an external 50MHz clock oscillator using clock buffer (1:2).
As per AN-1794 app note (http://www.ti.com/lit/an/snla101a/snla101a.pdf), operating on two separate clocks (in RMII slave mode) might introduce an uncertainty in the latency of the PHY receive datapath.
Is this applicable even when I am using same clock source to feed both PHY and MAC? We are aware that there is no physical clock connection from PHY to MAC (as in MII mode) in RMII mode.
If latency is introduced due to this type of clock topology, what is the maximum latency that can be expected in PHY datapath.
Regards,
Archana Rao
