Hi team,
I have a question for LOCK behavior.
#1
Is there a condition that LOCK is fixed low even though the input signal of FPD-LINK is correctly input?
It is assumed that the power supply the DS90UB926 correctly.
#2
How long does it take for LOCK to return after LOCK is temporarily lost due to disturbance noise?
When power is turned on, it is written in the data sheet that Lock is performed in a typical 5ms, max 40ms, but I care if it will take more time after loss of Lock due to signal quality deterioration after start.
#3
When the cause of LOCK loss is limited to the signal quality of FPD-LINK, what is the signal jitter condition where LOCK is lost?
For example, when jitter of 0.7 UI or more continues for several clocks or more.
We are checking in advance the conditions under which LOCK is lost.
We would like to define the behavior of each condition where Lock is lost regardless of the signal quality of FPD-LINK, and the condition where Lock is temporarily lost by signal quality.
Best regards,
Tomoaki Yoshida