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DS90UB926Q-Q1: Lock behavior and condition for lose lock

Tomoaki Yoshida91
Genius 5255 points
Part Number: DS90UB926Q-Q1

Hi team,

I have a question for LOCK behavior.

#1

Is there a condition that LOCK is fixed low even though the input signal of FPD-LINK is correctly input?

It is assumed that the power supply the DS90UB926 correctly.

#2

How long does it take for LOCK to return after LOCK is temporarily lost due to disturbance noise?

When power is turned on, it is written in the data sheet that Lock is performed in a typical 5ms, max 40ms, but I care if it will take more time after loss of Lock due to signal quality deterioration after start.

#3

When the cause of LOCK loss is limited to the signal quality of FPD-LINK, what is the signal jitter condition where LOCK is lost?

For example, when jitter of 0.7 UI or more continues for several clocks or more.

We are checking in advance the conditions under which LOCK is lost.

We would like to define the behavior of each condition where Lock is lost regardless of the signal quality of FPD-LINK, and the condition where Lock is temporarily lost by signal quality.

Best regards,

Tomoaki Yoshida

  • 0
    TI__Intellectual 1565 points
    Hi Tomoaki,

    1. With a valid FPD-Link input, LOCK should remain high.
    2. Up to 40nS for LOCK to go high from an unlocked state.
    3. Worst-case eye opening with LOCK high is 0.3UI, so jitter must be 1-0.3=0.7UI or less.

    This is system-level performance and can depend on:
    - PCB design
    - Cable selection and cable aging
    - Shielding & grounding
    - Proximity and strength of aggressor fields (radiated immunity, BCI tests characterize this)

    Mike
  • 0 in reply to Mike Leister
    Genius 5255 points

    Hi Mike-san,

    Thank you for your suuport.

    Regarding the answer No.2;

    It is us to 40 ns. Is it correct?

    I assumed up to 40ms.

    For example, If the Ser has stopped for 1 sec and then returns, does it mean that Lock will be recovered in 40 ns if the FPD-LINK signal is stable?

    Regarding the answer No.3;

    I understand that the jitter of the FPD-LINK signal needs to be 0.7 UI or less.

    0.7 UI is a reference of waveform quality, not the low / high threshold of Lock. Is it correct?

    For example, please let me know if there is a clear criteria for whether Lock falls to Low or if several pulses are continuous or the jitter increases by one pulse.

    I understand that waveform quality is affected by PCBs, cables, connectors, power supplies, etc.

    I want to understand what is the condition that CDR's PLL locks or unlocks.

    The LOCK is not specified in the data sheet, so we are investigating in what cases the Lock is lost and how it is affected by noise.

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida91
    TI__Intellectual 1565 points

    Hi Tomoaki,

    Worst-case lock time should be 40nS per the datasheet.

    Lock is dropped when the recovered eye opening is too small for the receiver to extract the clock.  Lock should be achieved with 0.3UI or greater eye opening.  I don't have a breakdown of the conditions that contribute to insufficient eye opening.

    Mike