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DS90UB933-Q1: ESD Test

Part Number: DS90UB933-Q1

Hi Sir 

Our Camera module use DS90UB933 ,so far ESD Test only can pass 1.5kV

Have any document to describe how to improve the ESD level ,our request is 8KV 

  • Hi Kai,

    What is the failure symptom?  Lock drop & black screen, screen flicker, one bad line on the screen?

    Some options

    • Power consumption can increase during an ESD event.  Make sure your power regulators are not browning out during the ESD test.
    • Try a DLW21SZ900HQ2L or similar common mode choke in the link path.  You can do this even with coax configuration, just outside the AC coupling caps.
    • Try a 2pF ceramic cap across the differential serial path near the AC coupling caps
    • New link cables that have been inserted less that 10 times perform better

    Mike

  • Hi Kai,

    Are you still debugging this?

    Mike

  • Hi Sir 

    1. Lock signal will drop 

    2. When the ESD test , the POC power supply not have any change or drop 

    3. Add a DLW21SN900HQ2 not improve the ESD performance 

    4. 2pF not improve 

    5. link cable will check later 

    Question 

    1. I saw datasheet have  ISO10605 test result ,what's the test method 

    2. Have any reference design pass the ESD 8KV test 

     

  • Hi Kai,

    Our ESD testing is done at the device level (ISO10605), the test method is described in the spec but does not apply to your system level ESD testing.

    I'll check to see if we have a TIDA reference design that has been tested for system level ESD.

    Mike

  • I've attached two links. 

    Here are items from a recent training:

    •Optimize AEQ/sFILTER
    –Use the ALP Margin Analysis tool to determine acceptable AEQ settings. Set AEQ/sFILTER min/max limits to allow only setting near the center of the “eye”.
    •Use the AEQ settings to increase the LOCK tolerance to errors (95x example).
    –Allow lock to establish with default AEQ settings
    –After Lock, Set 0xB9 to 0x3F. This increases the number of errors required for LOCK to drop. If this does not work, try the next three steps, one at a time.
    –Set 0x42(4) to 0x0. This stops parity errors from causing LOCK drop and is in line with how later parts operate.
    –Set 0x42(5) to 0x0. This stops packet encoding errors from causing LOCK drop.
    –Set 0x42(6) to 0x0. This stops FPD-Link Clock errors from causing LOCK drop.
    •We have seen immunity failures caused by power supply current limits. Check the voltage rails to make sure they stay in spec during the test. An optical probe is useful for this.
    •Try a common mode choke on the serial path if using STP/STQ. We use DLW21SZ900HQ2L.
    •Try adding a 10uF to 22uF ceramic cap from DC power to ground right at the DC connector.
    •Try a 2pF ceramic cap across the differential serial path near the AC blocking caps. If this works, check link margin to be sure it will work in the customers design.
    •Try a ferrite bead between cable shield and board ground. We have an experiment planned to quantify the effect.
    •Most of the time, you can get better BCI results without the EMC shield boxes.
    •Use EMC absorption sheets to narrow down where the vulnerable area is.
    •Use shielded connectors.
    Mike

  • Hi Mike 

    Anther question 

    Use the AEQ settings to increase the LOCK tolerance to errors (95x example) ==> I don't see it in DS90UB934 

  • You are right, those are available in the 936, not the 934.

    The rest of the tips and the two documents do apply to the 934.

    Mike

  • Hi Sir 

    Please refer to below our test method and result for 1KV

    1. Use DACAR462 cable to test 

    2. Could I config AEQ setting of DS90UB933 ? or only 936 or 954 could be modify 

    3. 2pF and 10uF can't improve 

    1KV ESD is very weak ,previous project use Maxim can pass at least 6kV
    Please provide your suggestion 

    Below excel is our ESD Test result 

    933 camera module ESD Solution list_2019_06_20.xlsx

    Our product ESD Test 

    https://youtu.be/CMu-CIrQHZM

    EVM ESD test 

    https://youtu.be/KnkQHW6LtoY

  • Hi Kai,

    Please try these 934 register changes, one at a time.

    • 934 register 0x02 bit 1 = 0
    • 0x05 and 0x06 registers set to 0xFF

    Mike

  • Hi Kai,

    Did the parity error threshold changes I mentioned June 25 improve performance?

    Mike

  • Hi Mike 

    We follow the suggestion to change the register ,but ESD still can't pass 1KV and change the serdes from 933 to 913 

    The ESD performance is the same (can't pass 1KV)

    Do you have any idea how to improve ?

    • 934 register 0x02 bit 1 = 0
    • 0x05 and 0x06 registers set to 0xFF
  • Hi Kai,

    It looks like it is layout/shielding related.

    Can you have your TI FAE open a helpme ticket and attach the schematic, layout, and mechanical drawing?  The helpme tool is private and will protect your IP.

    Mike

  • Hi Kai,

    As soon as you have your TI FAE submit a helpme ticket with your schematic and layout, please close this ticket so we switch to the private helpme ticket.

    Mike

  • Hi Mile 

    We have forward your information to local TI FAE

    Really appreciate your support  

  • Happy to help.  I just sent the FAE the link to our helpme ticket tool and will provide schematic/layout feedback through that private channel.

    Mike