Dear Support Center,
I am writing to ask about Jitter specification of RxCLKIN-/ +.
The following is described in Note 2 of the data sheet [6.6 Switching Characteristics] of the DS90CF386.
"Receiver skew margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows
for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 150 ps)."
If we comply with the [6.6 Switching Characteristics] table, do we need to meet the jitter 150ps requirement?
