I have a DS90CR482 part on a prototype board. The LVDS inputs are driven from an FPGA.
I am not using DC balanced mode. I am running with an 80MHz clock. I have verified that the input clock has a duty cycle of 4:3 (7.14ns high, 5.35ns low).
The output clock matches the input clock in frequency and duty cycle leading me to believe that the PLL is operating and locked.
All the LVDS input data lanes are at a state of constant '1'. LVDS common voltage is 1.2V.
None of the digital outputs are high.
What else should I check?
Thanks,
Jim
