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DS92LV18: DS92lv18 clok's

Jens Biltoft1
Prodigy 20 points
Part Number: DS92LV18
Other Parts Discussed in Thread: SN65LVDS100, SN65LVDS101

Hi

I am designing a Ser/DeSer board using the DS92LV18. I have added external logic with latches etc. to create a 64bit point to point multiplexer by using 2 identical boards and connect them with fibers.

I have actually 2 questions I hope someone can help me with.

I have an 25Mhz oscillator on the board. I intend to connect this clock to both the Tclk and the RefClk so that both the Tx side and the Rx side are clocked by the same oscillator.

Is this the correct way of using the DS92LV18?

Secondly I am having a bit of difficulties to find a level conversion circuit. The DS92LV18 has an LVDS interface on the DI+.DO- and RI+ and RI- pins. The fiber component I am using has LVPECL level interface. Can anyone help me with an application note on how to make this conversion?

Thanks in advance.

Regards

  • 0
    TI__Genius 10250 points

    Hello,

    The clocking scheme you described should be fine.  The requirement is that REFCLK on the DS90LV18 has to be the same (within 5%) as the TCLK on the other (transmit) side. Having TCLK and REFCLK on both sides the same should be fine.

    Regarding the PECL <-> LVDS conversion, you can use SN65LVDS100 & SN65LVDS101.  Please see the application section of the SN65LVDS100 datasheet for details.  Please notice that some optical modules have internal AC coupling capacitors.  The following 2 app notes have more details about interfacing PECL and LVDS with AC and DC coupling:

  • 0
    TI__Mastermind 43795 points

    Hi Jens,

    Making TCLK and REFCLK work at eactly 1:1 ratio is a good design practice.

    For level conversion there are several things to consider.

    1. Is your fiber solution AC coupled?  If yes, then the data you send across the fiber will need to be encoded or scrambled to maintain a DC balance.

    2. LVDS inputs Ri+/- can accept the LVPECL output levels.  Depending on the LVPECL output specifications, a simple 100 ohm differential load may or may not be enough.  In some cases there will need to be a DC termination path to GND as well, to bias the LVPECL outputs.

    3. The LVDS output levels are biased to a 1.2V common mode.  Most LVPECL input devices define a slightly higher input common mode voltage.  In this case a conversion or level shift would likely be needed.  If the LVPECL inputs are AC coupled, then no interface circuit would be needed.

    Regards,

    Lee