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DS90UB948-Q1: Internal test pattern generation CLK error

user5607380
Prodigy 70 points
Part Number: DS90UB948-Q1

Hello  TI Experts,

I am now using DS90UB948 with 1920x720 display but  the internal test pattern mode doesn't work well,there is LVDS output but CLK is wrong.

***2lane FPD-LinkⅢ Input, Dual Link OpenLDI Output***

The internal reference oscillator(nominally 200MHz) is integer divided  ( N=3 ) to generate the target pixel clock . The actual measurement LVDS output CLK is 23Mhz which should be close to 66.6Mhz.

Please help to confirm it.

Thanks.

Best regards.
Ray

  • 0
    TI__Guru** 103215 points

    Hello Ray,

    I am in the process of updating the app note on internal patgen to better reflect the frequencies across different devices. For 948 internal PATGEN, the source clock is closer to nominal ~130MHz and then divided down with the N value. For 1920x720 I would assume you need higher PCLK than 66.6MHz (is this 60 Hz?)

    Also note that if you are in dual OLDI mode, then each PCLK will be 1/2 the clock rate of the panel PCLK since the pixels are divided between two lanes. So ~23MHz makes sense if you are in dual OLDI mode because you have ~130MHz/3 = 43MHz -> dual mode divide by 2 = 21MHz which is close to what you are measuring. Please try N=2 and if you can't get the target frequency you can also try internal pategn from a serializer device going into 948 and then into the panel because the serializer devices use the 200MHz source clock.

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Prodigy 70 points

    Hi Casey,

    Thank you for your reply.

    "For 1920x720 I would assume you need higher PCLK than 66.6MHz (is this 60 Hz?)"-->It is 60 Hz. 

    The panel we used CLK is 44.1MHz as below. We need to get the 44.1MHz*2=88.2MHz frequency. For 948 internal PATGEN, the source clock is closer to nominal ~130MHz , it seems like can't get the target frequency. We will try internal pategn from a serializer device.

    Thanks.

  • 0 in reply to user5607380
    TI__Guru** 103215 points

    Hello,

    I think the larger problem may be that the resolution in your timings diagram is not 1920x720. According to your diagram, the active resolution is 960x720 which explains why the PCLK is lower. Make sure you adjust the PATGEN accordingly. 

    Best Regards,

    Casey