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LMH1983: LMH1983 PLL1 not exactly 74.25MHz

Paul Carson1
Prodigy 210 points
Part Number: LMH1983

Hi,

we have implemented an LMH1983 so we can GenLock to 720p50.

After power up send it several commands to set registers:

0x05 0x0C #5 DEVICE CONTROL Reset[7] Pwrdwn[6] AutoFormat[5] PLL1_mode[4,3] LOR mode[2] Force_148[1] OE[0]
0x07 0x06 #7 PLL2 FORMAT P.23 720p50 = code 6
0x09 0x02 #9 OUTPUT MODE P.34 Table 4 Crosspoint Selection = 0010 ; CLKout3 & CLKout2 = PLL2; PLL3 disabled
0x0A 0xCD #10 OUTPUT BUFFER CONTROL P.27 Enable CLKout2, CLKout1, Fout2
0x1B 0x06 #27 LOSS OF REFERENCE THRESHOLD 6 = 7 Hsyncs missed section 8.3.8 p17
0x1C 0x06 #28 LOSS OF LOCK THRESHOLD 6 section 8.3.6 p16
0x1D 0xDD #29 MASK CONTROL PLL2 & TOF2 enabled
0x20 0x06 #32 INPUT FORMAT P.23 720p50 = code 6
0x2E 0x10 #46 PLL2 ADVANCED CONTROL Divide by 2; output enabled
0x31 0x08 #49 PLL3 ADVANCED CONTROL PLL3_Disable[3]
0x34 0x28 #52 PLL4 ADVANCED CONTROL PLL4_Disable[3]
0x05 0x0D #5 DEVICE CONTROL Reset[7] Pwrdwn[6] AutoFormat[5] PLL1_mode[4,3] LOR mode[2] Force_148[1] OE[0]

We only need to operate from a 720p50 source at present and so have chosen to disable auto-detect.
We only need PLL2 outputting 74.25MHz to drive our HD-SDI Tx, hence the divide by 2 setting on PLL2.

Genlock disconnected:
PLL2 = 74.25MHz
0x00 reads 0x0A
0x01 reads 0xD0 (wrong format)
0x02 reads 0x20 (PLL2 locked)

Genlock connected:
0x00 reads 0x04
0x01 reads 0xC0 (correct format)
0x02 reads 0x30 (PLL2 + PLL1 locked)
PLL2= 74.2496MHz

If I set 0x05 = 0x09 then it does hold 74.2496MHz when I remove the cable and changes back to 74.25MHz when I set 0x05 = 0x0D

Do I need to manually adjust something else, perhaps 0x27 or 0x28 and if so will this be required per PCB in production?

I default design is to have Cs=1uF, Cp=47uF & Rp=17k4 but this is for NTSC (1716 clks/hsync).
I would like to calculate new values for 720p50(720 clks/hsync) but the datasheet formulas section 8.3.2 are conflicting for BW, the first formula includes 2 x PI()  but second formula (5+6) omits it, which is correct?

BTW, when I enable auto-detect it does recognise 720p50 input as it sets 0x20=0x06.

Using a BlackMagicDesin Sync generator.

Best regards,

Paul

0x05 0x0C #5 DEVICE CONTROL Reset[7] Pwrdwn[6] AutoFormat[5] PLL1_mode[4,3] LOR mode[2] Force_148[1] OE[0]
0x07 0x06 #7 PLL2 FORMAT P.23 720p50 = code 6
0x09 0x02 #9 OUTPUT MODE P.34 Table 4 Crosspoint Selection = 0010 ; CLKout3 & CLKout2 = PLL2; PLL3 disabled
0x0A 0xCD #10 OUTPUT BUFFER CONTROL P.27 Enable CLKout2, CLKout1, Fout2
0x1B 0x06 #27 LOSS OF REFERENCE THRESHOLD 6 = 7 Hsyncs missed section 8.3.8 p17
0x1C 0x06 #28 LOSS OF LOCK THRESHOLD 6 section 8.3.6 p16
0x1D 0xDD #29 MASK CONTROL PLL2 & TOF2 enabled
0x20 0x06 #32 INPUT FORMAT P.23 720p50 = code 6
0x2E 0x10 #46 PLL2 ADVANCED CONTROL Divide by 2; output enabled
0x31 0x08 #49 PLL3 ADVANCED CONTROL PLL3_Disable[3]
0x34 0x28 #52 PLL4 ADVANCED CONTROL PLL4_Disable[3]
0x05 0x0D #5 DEVICE CONTROL Reset[7] Pwrdwn[6] AutoFormat[5] PLL1_mode[4,3] LOR mode[2] Force_148[1] OE[0]
  • 0
    TI__Genius 16845 points

    Hi Paul,

    I don't believe additional register writes are required. In the typical application examples in the datasheet, the alignment control registers are also written during configuration, you might consider setting those as well.

    Equation 1 seems to have the factor of 2*pi for BW in radians, while equation 6 does not have the 2*pi so it would be frequency in Hz.

    Kind regards,
    Lane

  • 0 in reply to Lane Boyd
    Prodigy 210 points

    Hi Lane,

    thanks for your prompt response.

    Should have realised the rads ;-)
    I'm not using TOF at present an so have not addressed alignment, yet.

    PLL2 ouput frequency error:
    The 74.2946MHz could actually be measurement error as using a DSO, but I still need to understand why PLL2 output frequency changes with/without Genlock present?
    I would only expect the phase to change.

    Filter values:
    With the current (recommended) loop filter components my DF = 1.17 outside recommended 0.7071 to 1 range, should I change the Cs = 18uF, Rs=18k & Cp = 1uF?
    This will keep me inside 0.7071 < DF < 1 and BWppl1 < 13Hz (2 rad) with FB_DIV range 400-720. to allow 720p50/ 720p60 / 1080p50/ 1080p60.
    How critical are these limits?

    Is my calculation for Maximum BW correct = (27,000,000/720)/20 = 1875Hz, seems rather large?

    Thanks,

    Paul

  • 0 in reply to Paul Carson1
    TI__Genius 16845 points

    Hi Paul,

    Sorry for the delay in responding. I hope your issue is resolved.

    It appears PLL2 output frequency changes with/without Genlock because the device is configured to operate in Free-run mode on LOR. You would prefer to use LMH1983 is holdover mode. See datasheet section 8.4.4 for more info.

    It is better to change your loop filter components to the values that you determined. It is OK if your DF is not within this range, but the PLL may be unstable if there is not enough phase margin.

    Your calculation of maximum bandwidth is correct. The actual bandwidth calculated using equation 6 is much lower.

    Kind regards,
    Lane