DP83867IR: TskewR and IO_IMPEDANCE_CTRL

Hi Kenshow,

The default state of the DP83867 is to have internal delays enabled on the the RGMII bus. The timings mentioned in the datasheet are with the default internal delays enabled.

For your question about variation in impedance control, unfortunately we will not be able to provide that data. The range size and steps can vary with process so it is difficult to characterize the changes and the % accuracy of the steps.

-Regards

Aniruddha

Hi Aniruddha,

 I would like to know about more detail of question#1.

I understood as follows, but is it correct?

For TX signals (received to PHY), TsetupR and TholdR are specified by default as described in the data sheet  with the setting of RGMII_TX_DELAY_CTRL = 0111b (2ns). It is possible to shift the clock timing inside the PHY in the positive and negative directions by changing RGMII_TX_DELAY_CTRL.

I have another question about  RX signals (Transmitted from PHY).

Is the timing defined TsetupT and TholdT as same as above TX case? 

TsetupT and TholdT are specified by default as described in the data sheet  with the setting of RGMII_RX_DELAY_CTRL= 0111b (2ns). It is possible to shift the clock timing outside the PHY in the positive and negative directions by changing RGMII_RX_DELAY_CTRL.

Regards,
Kenshow

Hi Aniruddha,

Finally, what timing should we see to meet the RX and TX specifications between clock and data/ctrl?

I am considering RGMII of DP83867 instead of for the timing as follows. Is it correct?

If my considering is correct,  Are the timing values in this figure the default values ​​of RGMII_RX/TX_DELAY_CTRL included?

Regards,
Kenshow

Hi Aniruddha,

Do you have any update about the timing of RGMII specification for TI PHY?

Sitala processor was very simple specification as same as my previous post. Unfortunately, PHY data sheet are more confusing to our design.

Regards,
Kenshow

Hi,

Any update on this ?

Regards,
Kenshow