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DS90UB934-Q1: LOCK fail during EMC RI Radar band 1.2-1.4 G test

wang wang50
Intellectual 350 points

Part Number: DS90UB934-Q1
Other Parts Discussed in Thread: USB2ANY

HI ,  can you help to give some proposal ?  my issue : LOCK fail during EMC RI Radar band 1.2-1.4 G test   , it is  DS934 With DS913 , PCLK is 74.25MHZ .  power on coax . 

issue back ground : at beginning , lock fail  even at 50V/M  at 1.2-14G CW AM mode . after review with TI FAE , we disable DS934 AEQ  (0xD4) , then in 50V/M ,100V/M , we had pass with class A .

but in Radar PM2 modulation , it is still link fail during immunity  .   

we had reviewed with FAE on schematic and layout .  our coax cable is Dacar 302 .  we also use USB2ANY for  SI test .  we had pass our PCB  50 OHM characteristic impedance  test. 

thanks  .

  • 0
    TI__Intellectual 1565 points

    Hi Wang,

    Please try the following:

    • Program PAR_ERR_THOLD_HI and PAR_ERR_THOLD_LO to 0xFF.  This will increase the number of parity errors allowed before LOCK drops.
    • If that does not help, disable the parity checker RX_PARITY_CHECKER_EN.

    Are you using a shielded link cable connector?

    Mike

  • 0 in reply to Mike Leister
    Intellectual 350 points

    Hi Mike 

    thank you very much , I will try to set these parameters in7/23 , plz don`t close this issue before this time .

    and my connector is Fakra  , made by Ronsenberger .  it is shielded link cable connector . 

  • 0 in reply to wang wang50
    Intellectual 350 points

    HI Mike

     add a comment here : I had Modify the register and increase the bit error threshold that may reduce the 934 out of lock as well. (set 0Xb9 = 0x3f) .

    Parity threshold is for Parity error , is it related with PLL Lock ? 

  • 0 in reply to wang wang50
    TI__Intellectual 1565 points

    Parity error checks for data errors so is indirectly related to PLL lock.  If the PLL starts to unlock you will get parity errors.

    Rather than leave this ticket open for a month, can you close it and open a new one if there are still issues after your 7/23 testing?  You can link to this ticket for continuity.

    Mike

  • 0 in reply to Mike Leister
    Intellectual 350 points

    So , if it means  even if Parity threshold change to max , there is no impact to PLL unlock . because PLL unlock first ,then Parity error happens .

    I had open SSCG function  for DS934 , is it impact with PLL unlock ?

    thanks , I will close this ticket recently .

  • 0 in reply to wang wang50
    TI__Intellectual 1565 points

    Hi Wang,

    Correct.  PLL lock issues can cause data errors, but changing the error threshold does not impact the PLL.

    SSCG is within the PLL loop BW so the PLL can track the clock spreading without causing data errors.

    I look forward to helping again if there are follow-on questions after your 7/23 test session.

    Mike

  • 0 in reply to Mike Leister
    Intellectual 350 points

    HI Mike 

    thank you ,   i am sorry that  i did not described my question clearly .  i means : Parity  error won`t cause Link unlock events , am I right ?

    parity check is for data transition .  lock is for PLL clock .    so  even change  Parity threshold , it won`t resolve . 

    Sure ,i can try in the next days by myself . But I am  curious to know  if  how Parity error effect PLL  . 

    I had already made 0XB9 Link error count threshold. to maximum ox3F . it is fail . 

    So my question is  why Parity errors can cause PLL unlock ?  How does it effect ? base on the analysis we talked above . 

    Mike  , thank you for your help .

  • 0 in reply to wang wang50
    TI__Intellectual 1565 points

    Hi Wang,

    A parity error may cause different effects depending where the data is corrupted in the FPD-Link frame:

    • If the pixel data contains the error, a pixel may be received as the wrong color
    • If the data error occurs in the I2C back channel, a retransmit may be triggered.
    • If the data error occurs in the FPD-Link control bits, a display flicker may occur.

    As the field strength increases to the limit of system immunity:

    • Initially some parity/CRC error will be observed.
    • As the field is increased, these errors occur at a faster rate
    • As the field is further increased, lock will drop.

    Parity errors do not cause the lock to drop; but they are a warning that you are approaching the limits of immunity performance.

    Mike

  • 0 in reply to Mike Leister
    TI__Intellectual 1565 points

    Hi Wang,

    If further help is needed please let me know; if I have answered to your satisfaction please close this support ticket.

    Best regards,

    Mike