DS90UB953-Q1: 953/954-Q1 Hard Reset time spec

Kohsuke Hamasaki

Intellectual 1250 points

Part Number: DS90UB953-Q1
Other Parts Discussed in Thread: DS90UB954-Q1

Hi, Team,

I would like to ask why the Hard Reset time spec is specified in between High to High of PDB signal.

Do you think it should be PDB Low thresh to High thresh?

Thanks,

Best regards,

Koh

over 6 years ago

0 Charley Cai over 6 years ago

TI__Genius 12866 points

Hi Koh,

Are you referring to 953 datasheet section 9.1?

T3 hard reset time specs the minimal Low time.

Best Regards,

Charley Cai

0 Sally Cheung95 over 6 years ago

TI__Expert 5480 points

Hi Koh,

The DS90UB954-Q1 waits 1 ms after PDB goes high to allow time for power supply transients before sampling the MODE pin strap value and configuring the device to set the I2C address

Thanks,
sally

0 Kohsuke Hamasaki over 6 years ago in reply to Charley Cai

TI__Intellectual 1250 points

Yes,I refer the section 9.1 of 953 datasheet.

Which shows the T3 is defined as High to High. you mean it should be the LOW time which is LOW thresh to High thresh?

Thanks,

Best regards,

Koh

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DS90UB953-Q1: 953/954-Q1 Hard Reset time spec