This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Linux/TUSB7320: TUSB7320 WAKE# pin always in high state

Part Number: TUSB7320
Other Parts Discussed in Thread: TUSB7340

Tool/software: Linux

Hi,

We are using the following design to interface TUSB7320 in our board.

We have ensured that all the power up sequences are followed correctly. Also the 3.3V is enabled after 1.2V. But the WAKE# pin always in HIGH state and we couldn't able to establish PCI link. Are we missing anything in the design? Kindly help us to resolve this issue.

Thanks,

Koil Arul Raj.S

  • The TUSB7340 would have to be configured before it would drive a wake event.  Can you confirm the timing of the resets and why there are pulldowns on the clocks?  

    Regards,

    JMMN

  • Hi JMMN,

    Thanks for your response.

    The GRST pin is set high and OSC_CLK is enabled as soon as power to the PCIE block ON. As per code, the PRST signal is set HIGH, approximately 1.2ms after PCIE_CLK is enabled. Following figure displays the power up sequence order of important signals.

    Regarding the pull down on clock lines, It is done to satisfy the design recommendation of the processor used in our board. Do you find any discrepancy in our configuration and design. Kindly help us to rectify the issues.

    Thanks,

    Koil Arul Raj.S

  • Hi,

    Any updates on this.

    Thanks,

    Koil Arul Raj.S

  • The clocks look valid, can you confirm the GRST timing meets the requirements listed in Section 9.1.1 of the datasheet?

    Regards,

    JMMN

  • Hi JMMN,

    To meet the GRST# timings exactly as mentioned in the datasheet, we changed the hardware enable of GRST# to software enable using a GPIO.

    After modifying GRST#, we obtained the following power sequence timing diagram.

    Now all the signals are satisfying the timing requirement mentioned in the datasheet. But still the chip not enabling WAKE# signal. We are struggling to find the reason for the failure. What do you think?

    Thanks,

    Koil Arul Raj.S

  • Hi,

    Any updates on this issue.

    Thanks,

    Koil Arul Raj.S

  • Hi JMMN,

    Now we could able to enumerate PCI usb card with few hardware reworks. The lspci command gives us the following output.

    # lspci
    00:00.0 PCI bridge: Synopsys, Inc. Device abcd (rev 01)
    01:00.0 USB controller: Texas Instruments TUSB73x0 SuperSpeed USB 3.0 xHCI Host Controller (rev 02)

    But the xHCI host controller drivers are not properly loaded. The debug messages while booting are given as follows,

    [    1.888273] xhci_hcd 0000:01:00.0: enabling bus mastering
    [    1.888291] xhci_hcd 0000:01:00.0: xHCI Host Controller
    [    1.892282] xhci_hcd 0000:01:00.0: new USB bus registered, assigned bus number 1
    [    1.929749] xhci_hcd 0000:01:00.0: Host not halted after 16000 microseconds.
    [    1.935504] xhci_hcd 0000:01:00.0: can't setup: -19
    [    1.939090] xhci_hcd 0000:01:00.0: USB bus 1 deregistered
    [    1.943262] xhci_hcd 0000:01:00.0: init 0000:01:00.0 fail, -19

    On debugging we found that, in xhci_handshake() function present in xhci.c file throws error ENODEV(-19).

    I have enabled following options in the kernel,
    CONFIG_USB_XHCI_HCD=y
    CONFIG_USB_XHCI_PCI=y
    CONFIG_USB_XHCI_PLATFORM=y

    What is the reason for the above error? How to resolve this issue?

    Anticipating your response as soon as possible.

    Thanks,

    Koil Arul Raj.S

  • Hi Koil,

    TI does not support Linux drivers, have you tried updating to the latest kernel?

    Regards,

    JMMN