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DS92LX1621: Are GPIO0 & GPIO1 inputs sampled on falling edge of PCLK in forward direction?

David Brent
Prodigy 220 points
Part Number: DS92LX1621
Other Parts Discussed in Thread: DS92LX1622

We are using the GPIO[1:0] pins of the DS92LX1621 as additional parallel data inputs in the forward direction and are setting GPIO0 Config = 0x13 and GPIO[6:1] Config = 0x03. We expected GPIO[1:0] to be sampled on the rising edge of PCLK (TRFB = 1), like the other inputs are, but it appears GPIO[1:0] are sampled on the falling edge of PCLK. Is there an additional falling edge register on the GPIO[1:0] inputs, perhaps for synchronizing asynchronous inputs?

  • 0
    TI__Expert 4210 points

    Hi David,

    On the DS92LX1621, register 0x03[0] (TRFB) controls which edge the input is sampled on.

    Pixel Clock Edge Select:

    0: Parallel Interface Data is sampled on the Falling Clock Edge.

    1: Parallel Interface Data is sampled on the Rising Clock Edge.

    The default should be 0x03[0]=1, rising clock edge

    On the DS92LX1622, register 0x03[0] (RRFB) controls which edge the output is strobed out on.

    0: Parallel Interface Data is strobed on the Falling Clock Edge.

    1: Parallel Interface Data is strobed on the Rising Clock Edge.

    The default should be 0x03[0]=1, rising clock edge

    The GPIOs do not have a separate register; all inputs and outputs are sampled the  same.

    Perhaps you have more skew on the GPIOs?

  • 0 in reply to Darryl Jeong
    Prodigy 220 points

    Hi Darryl,

    We have TRFB = RRFB = 1 (defaults) but the GPIO[1:0] signals appear to have a different Tx and/or Rx latency in the forward direction (DS92LX1621 to DS92LX1622) relative to the other (DIN, HSYNC, VSYNC) inputs. We had to assert the GPIO inputs earlier than the others.