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DS90UB948-Q1: parameters configuration issue when using Jitter and Eye diagram Analysis Tools

Sherry Liang
Genius 10255 points
Part Number: DS90UB948-Q1

Dear team,

The following oscilloscope tests the eye diagram setting interface, about the PCLK/10 option, and what is the PCLK's frequency?
For example, our application, 949 and 948 pairing, two lane transmission, at HDMI side PCLK is currently set 154MHz, then what about the JTF BW frequency? It should be 154/10 = 15.4MHz, or 154/2/10 = 7.77MHz?

Could you please help answer this question?

Thanks & Best Regards,

Sherry

  • 0
    TI__Guru** 103215 points

    Hey Sherry,

    I guess you are talking about the output jitter on the FPD III interface? This is TDJIT in the datasheet. For dual lane mode, each lane should use PCLK/40 for the high pass filter setting. So for 949/948 at 154MHz, use a high pass filter of 154/40 = 3.85MHz

    Best Regards,

    Casey