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DP83867ERGZ-R-EVM: CLOCK_OUT

Hermann Demmelhuber
Prodigy 30 points
Part Number: DP83867ERGZ-R-EVM

Hello,

we are planning an application that includes 5 Phy's (DP83867ERGZR) (RGMII).

According to the datasheet the CLK_OUT-pin can be used as a reference clock for the next Phy. (See datasheet p. 23, rev. march 2017)

Is it possible to loop through the CLOCK-signal from Phy to Phy (CLOCK_OUT to XI -> 4 times)?

Is there anything which have to be considered (for example timing, startup behavior etc.)?

Thank you!

Best regards

Hermann

  • 0
    TI__Mastermind 23675 points

    Hi Hermann,

    It depends on the original clock source.

    The reason why you would be limited is due to accumulated jitter with the daisy chain.

    Generally, max allowed is one additional so that you still meet the IEEE specs.

    I suggest you do a stuff option to allow for both methods and see what the performance is with the clock source you pick.