This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83822I: WOL and EEE

Part Number: DP83822I

Hi,

I've read two paper about WOL and EEE below

http://www.ti.com/lit/an/snla261/snla261.pdf

http://www.ti.com/lit/an/snla265/snla265.pdf

1. my understanding is

for WOL: the PHY itself is not in low power mode, but the MCU/processor connected to the PHY is in low power mode.

for EEE: the PHY itself is in low power mode.

Low power mode here just refer to lower power consumption, but not a real mode.

Do I understand correctly?

2. In the paper it's said: By using WoL, backend equipment (i.e. FPGAs, Processors, ASICs, MCUs) can be powered-down until the PHY receives information that passes the specific frame detection criteria.

Do we have any special requirement for the backend equipment? I mean, the backend equipment itself should have the scheme to power down when no information is comming in through the PHY to support WoL, right?

3. Do the LED has dedicated status indicating for EEE or WoL? How can I achieve it?

  • Hi Howard Zhu,

    Yes your understanding is correct. EEE, phy goes in low power and it's Link Partner or Host SoC/MCU which controls PHY to be in low power/Active mode. EEE  feature is implmented in compliance to IEEE 802.3az and both DUT and Link Partner Phy has to be compliant to spec to work it.

    For WOL, Phy has to continously monitor WoL packets to indicate the Host. Host shall have power management system to wake-up on interrupt.

    Regards,
    Geet

  • For WoL, if we configure below.

    Does it mean that If PHY receive magic packet, COL voltage will change from high to low(falling edge) or low to high (rising edge).

    So we should configure the backend equipment (such as a processor) to be able to wake up through a rising or falling edge on a GPIO and connect this GPIO to COL pin?

    And for STEP6 below, why we need to clear level change? Both 1 to 0 and 0 to 1 is level change, right?

  • Hi,

    Yes, the GPIO configured to signal WoL signal changes the level ( the way it is configured). It has to be cleared to know PHY that MAC has interpreted the signal.

    Regards,

    Geet