DS954 working with DS953: CSI problem

Hello Xingzhu,

Can you please verify the high speed FPD Link datapath using the BIST feature and our MAP (Margin analysis program)? http://www.ti.com/lit/ug/snlu243/snlu243.pdf

Are you using EVM hardware or a custom design?

Best Regards,

Casey 

Hi Casey,

I check the BIST feature using these steps:

//954's i2c addr is 0x30, 953's alias addr is 0x04. 

//reset 953 except for reigster
i2cset -f -y 1 0x04 0x01

//reset 954 except for register
i2cset -f -y 1 0x30 0x01

//954 DEVICE_STS
i2cget -f -y 1 0x30 0x04
0xdf

//clear 953 error count
i2cset -f -y 1 0x04 0x49 0x28
i2cget -f -y 1 0x04 0x79     //this output 0x00
i2cget -f -y 1 0x04 0x52     //this output 0x45
i2cget -f -y 1 0x04 0x54    //this output 0x00

//read 954's b3
i2cget -f -y 1 0x30 0xb3    //this output 0x08

//enable BIST
i2cset -f -y 1 0x30 0xb3 0x01 //this will cause 953 can't be access through i2c

i2cget -f -y 1 0x30 0x5b //this output 0x30

i2cget -f -y 1 0x30 0x5c //this output 0x08

i2cget -f -y 1 0x30 0x57 //this output 0x00

If I change the BIST setting to:

i2cset -f -y 1 0x30 0xb3 0x09 //953 is ok with i2c connect

and 954's 0x57=0x00, 953's 0x54=0x00, 0x55=0x00, 0x56=0x00.

Does this means that 954/933 BIST is ok?

Best regards

Hello Xingzhu,

The BIST test must be disabled before the error counts can be read back. Pleas enable BIST in register 0xB3 by setting 0x01, then wait for the desired test time, and then disable BIST by writing 0xB3 = 0x00 and then read back the error count registers. 

Best Regards,

Casey 

Hello Xingzhu,

Any feedback on the above?

Thanks,

Casey 

Hello Casey,

       Sorry for late reply.

       I tried the way you said, enable BIST and wait for a desired time then disable BIST. The register read is:

      954's 0x57=0x00, 953's 0x54=0x00, 0x55=0x00, 0x56=0x00.

       I tried wait for different time from seconds to mininutes, the register values are the same as above, it seems no error occured in BIST.

Best regards

Hello Casey,

      After reading TI953's datasheet, I was wondering if you could help me with these questiones:
      1. our sensor data lane is 275Mbps, Is it compatible with 953?

      2. after 953 receive , for example, a line data, Does 953 confirm this long packet's CRC & ECC? if does, what will happen if CRC & ECC is wrong?

      3. Packet data from 953 to 954 is regenerated by 953? I mean, does 953 unpack data from mipi long packet, and regenerate a new packet with the same data to 954?

Thanks.

Best regards

Hello Xingzhu,

1. Yes the 953 can support up to 800Mbps/lane 

2. Yes the 953 checks the packet CRC and performs ECC. If there is an error it will be indicated in the registers of the 953 and the device can be programmed to send an alarm to the deserializer. The 953 will forward packets exactly as they are received including any errors.The DES can be programmed to forward error-ed packets, or to not forward error-ed packets.

3. When connecting a 953 with a 954, the packets are not unpacked. Each bit of the CSI-2 frame is simply mapped to the FPD encoding, sent to the other side, and then put back together. 

Best Regards,

Casey

Hello Casey, 

       We changed the sensor output lane speed to 400Mbps/lane，the data are correct now.

       It seems that using 275Mbps/lane is not ok, I'm not sure why this problem happens. 

       Can 953 support different lane speed automatictly? 'cause I didn't read instructions for lane speed configure in the 953's datasheet.

Best regards

Hello Xingzhu,

There is no configuration needed to change the lane speed for 953. Maybe the timing parameters from the CSI TX were incorrect at 275Mbps/lane?

Best Regards,

Casey 

Hello Casey,

        If the timming parameters from the CSI TX were incorrect at 275Mbps/lane, Does 953 will get some error?

        As mentioned before, in 275Mbps/lane, 953 did't show error, but 954 did. 

        I was wondering if 953/954 has different mechanism to detect csi error?

        Or if 954 has specfic data lane speed requirement for input data?

Best regards

Hello Xingzhu,

That is a strange issue and I'm not sure the reason. There is really no requirements for the lane speeds on either side as long as the number of lanes used and the per lane speed can accommodate all of the video bandwidth. So for example, if you were using four lanes on the 953 side with 275Mbps each, but only 2 lanes on the 954 side with 400Mbps each, then you would run into some issues, but other than that I'm not sure what could cause the problem you found. 

Best Regards,

Casey