Can someone confirm the state of the MII interface pins during reset for the DP83822H PHY transceiver.
We plan to interface two of these PHY's to a Sitara AM4377ZDN processor so we can implement an EtherCAT industrial network interface, however the MII pins on the processor for the first port are also used as the configuration pins for the processor and these will be driven via a buffer whilst the POR is active. During this time both the processor and PHY are held reset. When POR is released the processor activates however a warm reset output from the processor will keep the PHY's reset for a further couple of hundred millisecs.
On one particular evaluation board a couple of the MII lines were further isolated via an analogue switch, whereas on another this had been omitted and the buffer directly connected to the MII lines. The PHY datasheet isn't clear on the state of its output pins during reset...hence my question.
