SN65DPHY440SS: schematic check

Wayne Wang20

Part Number: SN65DPHY440SS

Hi team,

My customer is designing the SN65DPHY440SS schematic. Please see below picture. I already checked it and didn't find anything wrong. But hope you could also double check on it. Thanks.

Best regards,

Wayne

over 6 years ago

0 David (ASIC) Liu over 6 years ago

TI__Guru**** 176811 points

Wayne

Lane 0 is a special lane. DPHY440’s lane 0 is the only lane that supports the back channel. For this reason, DPHY440 lane 0 must always be connected to lane 0 of GPU and panel. If you don't plan to support the back channel communication, I would recommend connect to lane 1 and lane 2, and have lane 0 and 3 connected to ground.

Thanks

David

0 Wayne Wang20 over 6 years ago in reply to David (ASIC) Liu

TI__Expert 4380 points

Hi David,

Customer doesn't need the back channel function on Lane 0. But they have finished the PCB design so I just want to check with you that will Lane 0 have any bad impact on the normal communication function? Can they keep the current design? Is there any risk here? Thanks.

Best regards,

Wayne

0 David (ASIC) Liu over 6 years ago in reply to Wayne Wang20

TI__Guru**** 176811 points

Wayne

It depends on their application and this is why I recommend not to use lane 0 to avoid any potential issues.

If there is an issue, we do have SW workaround to work around the issue.

Thanks

David

0 David (ASIC) Liu over 6 years ago in reply to David (ASIC) Liu

TI__Guru**** 176811 points

Wayne

Do you have any additional questions or can this thread be closed?

Thanks

David

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SN65DPHY440SS: schematic check