The User Guide on SPI appears to be different from most other SPI protocols,

In most other documents, it said as this: If the clock phase is "0," then the receiver latches the data on the first transition of SCK from the idle state. If the clock phase is "1," then the receiver latches the data on the second transition of SCK, take Nvidia's Xavier for example.

But in TI's document, it is opposite like this: http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf, Table 2-5 and Figure 2-5 to Figure 2-8, include TMS320C672x, TMS320DM35x and other DSP.