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How to accurately predict DSI input to DP output delay

Dale Bengtson
Prodigy 20 points

Part Number: SN65DSI86

Hello,

I am investigating a design in which the delay from the DSI input to DP output is significant. 

Is it possible to accurately predict the time delay from the DSI input to the DP output (for example HSYNC-HSYNC of a given line)?  

Since the DSI and DP are operated from different clock sources (assuming the use of REFCLK), there must be a mechanism to account for the references moving with respect to each other.  What is the resolution of that correction mechanism?

Thank you

Dale

  • 0
    TI__Guru**** 187491 points

    Dale

    You can use HSYNC to calculate the delay from the DSI input to a DP output, but you also need a protocol analyzer on the DP side to decode the main stream data.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 20 points

    Hello David,

    Thank you for the reply.  To clarify, my question is regarding how to predict the delay so that we can determine whether this part will meet our needs before building HW.  I need to understand the delay and the jitter caused by the mechanism that adjusts for frequency error between the MIPI DSI and the internal PLL that generates the DP.

    Is it possible to predict that?

    Thank you,

    Dale

  • 0 in reply to Dale Bengtson
    TI__Guru**** 187491 points

    Dale

    For DSI86, it has an internal FIFO that buffers an entire single line (HACT) of data on the DSI input side, so the delay is the time to clock in the single line.

    The delay from input to output will be dominated by the delay through the buffer. I would assume time from HSYNC to HSYNC is the delay, but I don't have the data for this delay.

    Thanks

    David