Hi Team,
My customer has a concern on the application of DS92LV18, it seems Bus LVDS always use half duplex as below, but DS92LV18 can only cover full duplex in the datasheet. If DS92LV18 can support half duplex and support up to 1Gbps?
Thanks.
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Hi Team,
My customer has a concern on the application of DS92LV18, it seems Bus LVDS always use half duplex as below, but DS92LV18 can only cover full duplex in the datasheet. If DS92LV18 can support half duplex and support up to 1Gbps?
Thanks.
Hello,
Bus-LVDS can be full- or half-duplex. DS92LV18 is full-duplex, as you noted. In principle, you may be able to externally multiplex/demultiplex the half-duplex line and control DE and RE pins on DS92LV18. An external controller will have to control the multiplexer and the DE and RE inputs to DS92LV18. However, this won't be optimal or efficient operation, because whenever you switch from transmit to receive and enable the receive path, the DS92LV18 receiver will have to resynchronize again to recover the clock (please see "Resynchronization" section on page 13 in the datasheet). This resync will also happen on the other side, but the control may be internal inside the FPGA.
Regards,
Yaser