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DP83848I: TX CLK duty cycle doesn't match with processor requirement

Remya R
Prodigy 180 points
Part Number: DP83848I

Hi,

We are designing a communication bridge device based on the MCU MC68360 from NXP and a TI based Ethernet controller DP83848I.We are using SNI interface for the same. But when we look into the CLK duty cycles requirement The TX CLK duty cycle of DP83848I is 25ns,75ns ( TCLK width Low, TCLK width High) whereas in our processor , MC68360 it is required as (45ns ,40ns) min. So do you have any option to change the duty cycle of TX CLK to( 50ns,50ns)? We are not sure whether we can go ahead with our design.Could you please confirm on this?

  • 0
    TI__Mastermind 18425 points

    Hi Remya,

    TX_CLK timing mentioned in the datasheet is a input requirement of the PHY. There is no provision to change the timing characteristics of the PHY for input or output. Is the issue here that the output of the processor is out of bound for the PHY input ?

    -Regards

    Aniruddha

  • 0 in reply to Aniruddha Khadye
    Prodigy 180 points

    Hi Anirudda,

    Thank you for your support!

    In my understanding TX CLK is the output of the PHY and which is the input for our processor.ywa

    Anyway, now our processor is working, but when we look theoretically it is out of bound with processor input. May be in some marginal it is working now. But our concern is it cause any issue in future.

    Is there any other chip recommendation with TX CLK and RX CLK having 50:50 duty cycle and support SNI interface?