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DS90UB954-Q1: How to config UB954 with 2 lanes when connects to UB953/imx390

Xiaodong Hu
Prodigy 20 points
Part Number: DS90UB954-Q1

Dear

We have a system with Sony image sensor IMX390 12bits raw output, 4 csi lanes I think. The deserializer is UB954 which only has port0(two lanes) connect to host cpu csi ports.

The data path is  : IMX390 ->TI953->TI954->2lane output -> CPU. So is it doable 953 config to 4 lanes, but 954 only use 2 lanes?

If the design is good, can I get the register setting of Ti954?

Thanks,

Xiaodong

  • 0
    TI__Guru** 108100 points

    Hello Xiaodong,

    I believe you are okay with just 2 lanes at the 954 output since this is enough for your sensor.

    If you want to enable 4 CSI-2 lanes then you need to write in the 954 reg 0x33[5:4]=00

  • 0 in reply to Hamzeh Jaradat
    Prodigy 20 points

    Hi Hamzeh,

    Thank you for your answer.

    One more question, does this setup will affect the frame resolution cpu csi port received? I am asking because the image sensor frame is 1936x1100, I read 0x73-0x76 registers, line counter is 2904, which matches to 1936*12/8=2904, but line length is only 1044, which means frame width is only 696, almost half of expected. I also got "CHANSEL_SHORT_FRAME" from log. Is my calculation right? So does it mean frame got chopped or re-sized when image sensor has 4 lanes to 953, but 954 only has 2 lanes out to cpu csi port? 

    Please advise, thanks.

    Xiaodong

  • 0 in reply to Xiaodong Hu
    TI__Guru** 108100 points

    Hello Xiaodong,

     

     Using 2 lanes or 4 lanes at the 954 CSI output does not affect the received data or outputted data.

      

    Also you can use 2x lanes at 953 Input and 4x lanes at 954 output, or vice versa... they are independent from each other!

    You only need to take care if you use 2x lanes at 953 input that this has enough bandwidth for Image sensor data.