CCS/DP159RSBEVM: DP159RSBEVM can support to HDMI 4K@60Hz

Lawrence

DP++ V1.1 Type 1 supports HDMI up to a 165MHz TMDS clock rate while Type 2 supports HDMI up to a 300MHz TMDS clock rate. DP159 supports both Type 1 and Type 2.

YUV 4:2:0 4k @ 60 Hz and RGB 4k @ 30 Hz need 297 MHz. 

Can you please dump out the DP159 registers? In particular, the TMDS_CLOCK_RATIO_STATUS bit in register 0x0Bh.

Thanks

David

Hi, David

register we will check, DP159 can support HDMI 2.0?

If any, Please advise me.

Thanks,

Best regards,

Lawrence.

Hi, David

we saw the datasheet, DP159 can support DP++ V1.1 (up to 300Hz), it`s means can support  HDMI1.4 right?

how to setting can support HDMI2.0

If any, Please advise me.

Thanks,

Best regards,

Lawrence.

Lawrence

HDMI2.0[3] standard requires the transmitter termination impedance should be between 75 to 150-Ω. Older versions of the HDMI standard required no source termination. For HDMI1.4b[2] when data rate over 2 Gbps, the output performance could be better if the termination value between 150 to 300-Ω which was allowed. The SNx5DP159 supports three different source termination impedances for HDMI1.4b[2] and HDMI2.0[3]. Pin 36, TX_TERM_CTL, offers a selection option to choose the output termination impedance value. This can be adjusted by I 2C[4]; reg0Bh[4:3] TX_TERM_CTL.

As part of discovery, the source reads the sink’s E-EDID information to understand the sink’s capabilities. Part of this read is HDMI forum vendor specific data block (HF-VSDB) MAX_TMDS_Character_Rate byte to determine the data rate supported. Depending upon the value, the source will write to slave address 0xA8 offset 0x20 bit1, TMDS_CLOCK_RATIO_STATUS. The SNx5DP159 snoops this write to determine the TMDS clock ratio and thus sets its own TMDS_CLOCK_RATIO_STATUS bit accordingly. If a 1 is written, then the TMDS clock is 1/40 of TMDS bit period. If a 0 is written, then the TMDS clock is 1/10 of TMDS bit period. The SNx5DP159 will always default to 1/10 of TMDS bit period unless a 1 is written to address 0xA8 offset 0x20 bit 1. When HPD_SNK is de-asserted, this bit is reset to default values. If the source does not write this bit the SNx5DP159 will not be configured for TMDS clock 1/40 mode in support of HDMI2.0. As the SNx5DP159 is in link but not recognized as part of the link it is possible that the source could read the sink EDID where this bit is set and does not re-write this bit. If the SNx5DP159 has entered a power down state this bit is cleared and does not reset on a read. To work properly the bit has to be set again with a write by the source.

Thanks

David

Hi David,

The pin36 TX_TERM_CTRL you mentioned exist on SN65DP159RGZ.

Is any to configure ths Termination on SN65DP159RSB?

The other question is, how do we set SN65DP159RSB EVM to output HDMI2.0 (4K @60Hz) when we input DP (4K @60Hz) signal into EVM?

Johnny

In pin strap mode, TX_TERM_CTRL pin needs to be floating and it will then automatically selects the termination impedance base on the data rate.

DP or DP++? DP159 only support DP++, not DP. For DP to HDMI, you would need an active protocol converter.

Thanks

David

Hi David,

DP159RSB has no TX-TERM_CTRL pin. Could we set this pin through I2C?

Information correct, DP++ is implemented in our current System.

By connecting DP++ (Output Resolution 4K @60Hz) to DP159RSB EVB, than output HDMI to monitor, the monitor shows the resolution 4K @30Hz.

Johnny

Johnny

You can set the TX_TERM_CTL through register 0x0Bh. 

For HDMI1.4, TX_TERM_CTL needs to be set to NO Termination or 150 to 300ohm.

For HDMI2.0, TX_TERM_CTL needs to be set to 75 to 150ohm.

Would you please dump out both Page 0 and Page 1 registers?

Page 0 registers are already included in the datasheet.

You can access Page 1 registers by writing 0x01 to register 0xFFh first.

Thanks

David

David, 

The register as above pics. I dump this register by using TI "EyeScan Tool"

When we set TMDS Clock Ratio to "1/40 of TMDS bit period", the monitor will have no output. 

We tried to measure HDMI clock from DP159RSB EVM. the clock is around 75MHz. 

After we change the TMDS clock Ratio back to 1/10 of TMDS bit period, the monitor has output (4K @30H), the clock is 296MHz. 

Johnny