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TL16C752D: Delay from stop to interrupt of TL16C752D and TL16C752B

Part Number: TL16C752D

Hello,

I have a question about the contents of the thread below.

https://e2e.ti.com/support/interface/f/138/p/542016/2247137

Please tell me about Delay from stop to interrupt.

・TL16C752B: 100[ns]
・TL16C752D: 1[baudrate]

I understand that this change is not a mistake but a correct change.
However, in the above thread, it ends with the content of confirming whether it is a mistake or not.

May I recognize that Delay from stop to interrupt of TL16C752D is 1[baudrate]?

Best Regards,

Kaede Kudo

  • Hey Kaede-san,

    I have a TL16C752D (internal EVM) I do test and get back to you on this. My initial experience with supporting this device tells me it is probably asynchronous (there was an e2e post from someone previously who I believe confirmed this through testing, I can't seem to find the post though.). Sometimes maximum limits in datasheets are padded such that it gives us more margin, this could be one of those cases.

    I likely won't have time to confirm this until early next week. Is that okay?

    -Bobby

  • Hello Bobby-san,

    Thanks for your comment.
    I will wait for your update.
    I appreciate your cooperation.

    Best Regards,

    Kaede Kudo

  • Hey Kaede-san,

    I'm going to try to set up my board tomorrow to check this for you if everything works out correctly, I can get you results tomorrow.

    Sorry for the delay.

    -Bobby

  • Hello Kaede-san,

    I just finished making measurements and here is what I found.

    I sent 0xAA and measured the low time for a slower baud rate and measured 42.77us:

    From this I shifted cursor B to ~42.77us from cursor A to measure the stop bit (only 1 stop bit). I then shifted cursor A ~42.77us from where cursor B was and looked to see if we were below 42.77us.

    From this, we can see the INT triggers in the microsecond range and is below the 1 baudrate max we spec.

    I repeated this at a higher baud rate as well:

    From this I would say that our device actually does trigger it's INT based on the baudrate and that it should always be less than 1 baudrate. It does NOT have a sub 100ns asynchronous max time like the B version.

    -Bobby

  • Bobby-san,

    Thank you for your cooperation!

    I understood about  Delay from stop to interrupt of TL16C752D is 1baudrate(max).

    Excuse me, but please let me ask you a few more questions.

    I have been inquired by my customer that there is the following phenomenon.
    When I observed the waveform of T16C752D D / S, p12 Transmit Timing, 2 pulses were output from INT.

    * Can something like this happen?
    * What is the cause if it happens?
    * What should I check with the customer?

    Best Regards,
    Kudo

  • I have been inquired by my customer that there is the following phenomenon.
    When I observed the waveform of T16C752D D / S, p12 Transmit Timing, 2 pulses were output from INT.

    * Can something like this happen?

    Do you have a scopeshot of this occurring? what is the time difference between the first pulse and second? Is the INT trace on the PCB close to any other fast edge rate traces?


    * What is the cause if it happens?

    Cross talk is my initial guess, essentially parasitics in the traces of the PCB. What is the value of the IER register? It could be possible they service an INT and an another INT gets tripped around the same time.
    * What should I check with the customer?

    Please see my questions above.

     

    -Bobby

  • Bobby-san,

    Thank you for your reply.
    And I'm sorry for my late reply.

    I have sent your comment to my customer, but no feedback has been returned from the customer.
    I'll contact you again when I get feedback.

    Best Regards,

    Kaede