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Original question:

DP83867E: Clear Configuration Register

DP83867E: Confirm Sequence Order is Correct

Mitchell
Expert 4915 points
Part Number: DP83867E

Hi Team, 

This is in follow-up to a previous question. 

For the DP83867 SW is doing the following:

Timestamp

Register write

Notes

7.8

-----

RST_B goes high

13.59132826

0x1F <= 0x8000

[14] - SW reset

13.59964824

0x31 <= 0x0130

[7] - Clear bit 7 for bootstrap fix

13.61160822

0x00 <= 0x1140

[12] - Auto-negotiation enable;
[8] - Full duplex operation
[6, 13] - Speed select = 1000 Mbps

14.61520678

0x09 <= 0x0300

[9] - Advertise 1000Base-T full duplex
[8] - Advertise 1000Base-T half duplex

15.60952823

0x1F <= 0x4000

[14] - SW restart

We've moved the SW RESTART to the end of the order, such that it's the last thing we do. Can you confirm that this sequence order is sufficient?

Thanks,
Mitchell