SN65DSI86: DSI86 REFCLK Setting

Vincent

I sent you the spreadsheet, please check.

Thanks

David

Hi David,

We also have some questions as below

Vincent

1. You can use DSI to configure DSI86 CSR. When used to configure the DSI86, all communication from the DSI86 to the GPU (read responses) will use DSI channel A lane 0 in LP signaling mode. But I would recommend using the I2C to access the DSI86 CSR since the I2C is always available.

2. You can disable ASSR by pulling TEST2 pin high, and then execute the 4 lane code in question 1 to disable ASSR control

3. Right pixel start is 1369

4. Please refer to the color bar pattern in register 0x3Ch.

5. LEFT_CROP and RIGHT_CROP are both set to 0

6.The calculation looks correct.

7. Attached is the example configuration script file based on the Samsung EDID info with color bar enabled.

<DSIInitSequence> 
23 FF 7 \n 
23 16 1 \n 
23 FF 0 \n 
23 0A 2 \n 
23 10 80 \n 
23 12 64 \n 
23 13 64 \n 
23 94 E0 \n 
23 0D 1 \n 
FF 0A \n 
23 5A 4 \n 
23 93 20 \n 
23 96 0A \n 
FF 14 \n 
23 20 58 \n 
23 21 05 \n 
23 22 58 \n 
23 23 05 \n 
23 24 20 \n 
23 25 07 \n 
23 2C 20 \n 
23 2D 00 \n 
23 30 05 \n 
23 31 00 \n 
23 34 8C \n 
23 36 39 \n 
23 38 30 \n 
23 3A 02 \n 
23 5B 0 \n 
23 3C 17 \n 
23 5A 0D \n 
</DSIInitSequence> 

Thanks

David 

Hi David,

Vincent

Hi David,

We can't output test pattern in DSI86 now. There is no error mark in IRQ status register.           
All the registers dump out are correct. PLL Lock is successful.          
How to check this issue? (All registers without error messages)?

Vincent

Would you please dump out register 0xF0h through 0xF8h? 

Does the panel support the ASSR? If not, do you have the TEST2 pin pulled high?

Thanks

David

Hi David,

Could you give me a example for this SHARP’s panel 2880 * 1920 include EDID

We don’t sure how to input the "Main_Inputs_Page"

Vincent

Please follow the instruction in the first page of the spreadsheet. You use the EDID format page to input the EDID info, and then copy and paste into the main input page.

Sharp_PANEL_VIDEOREGISTER_CALC.zip

Thanks

David

Hi David,

We can show the test pattern in SHARP panel now.
Before we also can MIPI to eDP in Samsung panel.
We use the same MIPI setting only change the resolution and DSI CLK in Qualcomm.
The DSI CLK is 565 MHz, so we change the DSI86 0x12 and 0x13 to 71.
But can't work.

Error as below

F0 01
F1 2F
F6 42

Could you help us to check this issue?

Hi David,

We can show the test pattern in SHARP panel now.
Before we also can MIPI to eDP in Samsung panel.
We use the same MIPI setting only change the resolution and DSI CLK in Qualcomm.
The DSI CLK is 565 MHz, so we change the DSI86 0x12 and 0x13 to 71.
But can't work.

Error as below

0xF0 01
0xF1 2F
0xF6 42

Could you help us to check this issue?

Hi David,

We can output the test panel in SHARP panel now.
But we can't output from MIPI input.
Before we use the Samsung panel and use the same platform (Qualcomm), it can output from MIPI input.
We use the same MIPI setting, change the MIPI Resolution and Pixel Clock for SHARP panel.
The DSI CLK is 565.63MHz, we had change the DSI86 register 0x12(DSIA Clock) and 0x13(DSIB Clock) to 71.
But it can't output.
Could you help us to check it? below is error status, thanks!

F0 01
F1 2F
F6 42

Vincent 

Are you using both DSI channel A and B?

Instead using the Samsung MIPI setting, can you please using the MIPI setting in the spreadsheet I sent to you yesterday as long as the spreadsheet DSI input condition matches with your hardware DSI configuration? 

Thanks

David

Hi David,

Yes, we use both DSI channel A and B.

Below is our setting, about the hardware, it is only change the panel.

Vincent

Could you please dump out the entire DSI86 register for me to review?

Thanks

David

Hi David,

We can display the panel now.

But we have two problems as below.
1. Boot-up display screen is placed for a period of time. After a period of time, only have the backlight but not have displayed.
2. There is a probability that the screen will not wake up if it is repeatedly turned on or off. (SamSung and Sharp have the same issue)

For the probabilistic wake-up problem, the software reset is executed. Then the initialization I2C configuration is executed. The screen can be displayed.
Test pattern have the same issue.

Could you help us to check it?

Vincent

For #2, does the DSI86 gets turned off as well?

You can try to add a line of code here to see if it helps

======Start Semi-Auto Link Training ======

<i2c_write addr=0x2D count=1 radix=16> 96 02 </i2c_write> <sleep ms=20/>

<i2c_write addr=0x2D count=1 radix=16> 96 0A </i2c_write> <sleep ms=20/>

Assuming the issue is related to the link training, the other option is to change the pre-emphasis and SWING level in the DP Link Training LUT registers.

If the panel supports fast link training, you can change the DP main link training from semi-auto training to fast link training. Please see section 8.4.5.7.2 for detail on the fast link training.

Thanks

David

Hi David,

What conditions DP_PLL will from lock to unlock?

Vincent

Please probe the clock at the DSI_CLK or the REFCLK input and make sure the clock is within the DSI86 PLL requirement.

Thanks

David

Hi David,

We put the set in temperature chamber.
The panel don't have display when DSI86 about 72°C.
We have use the panel Internal pattern is OK, DSI86 use test pattern still is fail.
Could you help us to check this issue?

We read the 0xF4 is 41

How to check the status from EDID?
How to fill in the AUX_ADDR?

Vincent

The DSI86 reported I2C-over-AUX or native AUX failure.

Can you please read the EDID and see if the EDID you read match with the panel EDID info?

To read the EDID, please follow the procedure in section 8.4.5.3

Thanks

David