DP83822I: What may cause RX_CLK change to 6.94MHz

Hi,

This is very unusual. Are you able to link-up, transmit data over MAC interface when you see this phenomeno ?

Regards,
Geet

Hi Geet,

  NO. We can only read register data through MDC / MDIO interface. Below is the power up timing sequence I captured, I may need your support below,

• When will be Bootstrap pin sampled? On the rising edge of RESET or when RESET is on low level? Please help check if this power up sequence. (VDDIO=VAVDD)
• What may cause RX_CLK frequency change to ~7MHz?

   Thanks.

Hi,

Above has big glitch on VDDIO. Can you please ensure that VDDIO is ramped completely ?

Regards,
Geet

YES. And I find that the power is the main cause to the PHY to get into an unnormal state, which can lead the clock frequency to ~7MHz. If I used external 3.3V, the issue is no longer exist. Do you have some idea about why the power can cause this issue? Thanks.

Hi Geet,

   Could you please share me what is the requirement, on which page? And Why the clock frequency will be 6.94MHz?

Hi,

Device is characterized as per the specification defined in datasheet. Power Ramp Timing are defined in  Power on Reset section.

Behaviour of device operating out side the specification is not characterized and we can not comment why RX_CLK is 6.94 MHz. 

Regards,
Geet