i am unable to write to registers above 31 (0x1f) using Intel FPGA triple-speed-ethernet MAC module using MDIO indirect access. i can read/write to registers below 31.
the design engineer did not strap the device at all assuming all configuration can be done via MDIO.
Are there any straps mandatory for MDIO to access all registers ?
Sample code below:
IOWR_ALTERA_TSEMAC_MDIO_ADDR0(tseMAC, 0x0a);
// MMD=0x01, register=0x6f, data=0xdd0b
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0d, 0x001f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0e, 0x001f); // Reg Addr
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0d, 0x401f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0e, 0x8000); // Reg value
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0d, 0x001f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0e, 0x001f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0d, 0x401f);
reg_status = IORD_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x001f);
printf("PHY Addr: 0x001f, Reg: 0x%x.\n", reg_status);
// MMD=0x01, register=0x6f, data=0xdd0b
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0d, 0x001f); // Dev Addr
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0e, 0x0000); // Reg Addr
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0d, 0x401f); //
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0e, 0x0140); // Reg value
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0d, 0x001f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0e, 0x0000);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0d, 0x401f);
reg_status = IORD_ALTERA_TSEMAC_MDIO(tseMAC, 0, 0x0000);
printf("PHY Addr: 0x0000, Reg: 0x%x.\n", reg_status);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0d, 0x001f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0e, 0x0032); // Reg Addr
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0d, 0x401f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0e, 0x00D3); // Reg value
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0d, 0x001f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0e, 0x0032);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0d, 0x401f);
reg_status = IORD_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0032);
printf("PHY Addr: 0x0032, Reg: 0x%x.\n", reg_status);
// MMD=0x01, register=0x6f, data=0xdd0b
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0d, 0x001f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0e, 0x001f); // Reg Addr
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0d, 0x401f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0e, 0x4000); // Reg value
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0d, 0x001f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0e, 0x001f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0d, 0x401f);
reg_status = IORD_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x001f);
printf("PHY Addr: 0x001f, Reg: 0x%x.\n", reg_status);
