Hi,
We've build a transmission system consists of Intel FPGA, optical fiber, TLK 10232 and Xilinx FPGA. The data firstly been sent from Intel FPGA to optical module by using KR. Than the optical modules on two chip transmit the data through optical fiber. The TLK10232 treceives the data from optical module then sends it to the Xilinx FPGA that on the same chip with TLK10232. The problem is that we find error code during this process. After several tests on this system, we assumed that the error code might occured at the optical module part or at TLK10232 receiving part. I'll breifly list out our tests to you to knew better of the transmission system I described.
we have another two former applications with similar contruction mentioned above and three test paths without error code.
1. Xilinx FPGA <-(XAUI)-> TLK10232 <-(KR)-> 10G optical module <--> optical fiber <--> 10G optical module <--> TLK10232 <--> Xilinx FPGA
2. Xilinx FPGA <-(KR)-> 10G optical module <--> optical fiber <--> 10G optical module <--> TLK10232 <--> Xilinx FPGA
3. Intel FPGA <-(KR)-> 10G optical module <--> optical fiber <--> 10G optical module <--> Intel FPGA
4. Xilinx FPGA <-(KR)-> 10G optical module <--> optical fiber <--> 10G optical module <--> Intel FPGA
5 .Xilinx FPGA <-(KR)-> 10G optical module <--> optical fiber <--> 10G optical module <--> Xilinx FPGA
All five transmission tests are all with correct functionality and without error code. Nevertheless, if I write the path with error code in format of above like "Intel FPGA <-(KR)-> 10G optical module <--> optical fiber <--> 10G optical module <--> TLK10232 <--> Xilinx FPGA" you can easily find out that compares to the five paths mentioned above, the error could only happens at optical module to TLK10232 or at FPGA to optical module. Therefore, we want to ask you that if you have any advice or solution on this problem?
Futhermore this is our configuration of TLK10232:
07.0000 = 2000 (clode self-negotiate)
01.0096 = 0000(clode link training)
01.00AB = 0003 (open FEC)
Best Regards,
Qi