I am NOT able to write to registers above 31 (0x1f) using Intel FPGA triple-speed-ethernet MAC module using MDIO indirect access. i can read/write to registers below 31.
the design engineer did not strap the device at all assuming all configuration can be done via MDIO. Yes/No ?
Are there any straps mandatory for MDIO to access registers above 31(0x1f) ?
Sample code below writes to register 0x32 the value 0xD3 but reads back 0x0 :
IOWR_ALTERA_TSEMAC_MDIO_ADDR0(tseMAC, 0x0a);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0d, 0x001f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0e, 0x0032); // Reg Addr
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0d, 0x401f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0e, 0x00D3); // Reg value written 0xD3
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0d, 0x001f);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0e, 0x0032);
IOWR_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0d, 0x401f);
reg_status = IORD_ALTERA_TSEMAC_MDIO(tseMAC, 1, 0x0032);
printf("PHY Reg: 0x0032, value: 0x%x.\n", reg_status);
The value read from register 0x32 was 0x0000
