TMDS181: Design can not receive data of 4K correctly.

Is there any update?

Regards,

JMMN

Luck

I will close this thread for now, you can re-open the thread by replying to it or creating a new thread.

Thanks

David

Hi JMMN:

Sorry for my delay reply, since I was on annual leave last week.

I confirmed with customer theFPGA output DP++, and they refer the EVM of FPGA design.

And they check the software is OK on EVM.

Pls. give some advice.

altera_fmc_hdmi_rev11.pdf 

Hi David:

Pls. help to not close the post, since I was on annual leave last week.

Luck

Would you please dump out TMDS181 Page 0 and Page 1 registers? Page 0 registers are included in the datasheet. For Page 1 registers, please write 0x01h to address 0xFFh first, and then dump out the registers.

Thanks
David

Luck:

    Can you dump register information to David?