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DS90UB954-Q1: DS90UB954 GPIO for debug

paulmcw
Intellectual 295 points

Part Number: DS90UB954-Q1

Hi,

I'm trying to use the 954 GPIO pins for debug but am having difficulty in correlating the results.

I have GPIO pins configured to output FV and LV signals for an incoming FPD port to a remote 953 

I am testing the attached sensor with varying frames sizes but have noticed that my settings do not always correlate with values signals reported by 954.

It would be helpful if you could explain the following:

1. 954 registers (0x75,76) report line count as 1080 - but the LV signal is toggling 2160 times during FV assertion.

2. 954 registers (0x75,76) report line count as 1620 - LV signal is toggling 1620 times during FV assertion.

The datasheet indicates that each long packet will be counted as a video line.  If this is true it would seem that each CSI-2 long packet may only contain half the video line data.

This seems to contradict the sensor datasheet.

Can you please clarify exactly what the LV signal indicates? Does it identify video lines or packet boundaries?

Also, I'm wanting to synchronise the video streams on the each of the 953 ports of the 954.

I can configure a GPIO to indicate if synchronisation has been achieved.  The output resulting signal is pulsed - does this indicate correct synchronisation or should the signal remain permanently high to indicate synchronisation.?

Thanks

Paul 

 

  • 0
    TI__Genius 11340 points

    Hi Paul,

    The FrameValid (FV) and LineValid (LV) indications from the Receive Port indicate approximate frame and line boundaries at the FPD-Link III Receiver input. These signals may not be accurate if the receiver is in CSI-2 input mode and multiple video streams are present at the Receive Port input. Are you using multiple VC IDs received on a single port?

    Another question that I have regarding your observation:

    1. 954 registers (0x75,76) report line count as 1080 - but the LV signal is toggling 2160 times during FV assertion.

    -> can you double check if you miscounted the FV? The LV signal is exactly twice as much as the line count?

    2. 954 registers (0x75,76) report line count as 1620 - LV signal is toggling 1620 times during FV assertion.

    -> this looks correct.

    Best,

    Jiashow

  • 0 in reply to Jiashow Ho
    Intellectual 295 points

    Hi Jiashow,

    Thanks for the prompt reply. 

    I am currently trying to forward two video streams, on the 954 CSI-2 port, using line concatenation.  The streams are sourced from two identically programmed image sensors connected to remote 953's.

    Each sensor is only sourcing one video stream.

    When a single stream is forwarded to a downstream device the video is observed.

    However, when both streams are forwarded using line concatenation the video signal is stopped by the 954 after approx 10 long packets when scoping the CSI-2 signal.  This repeats every frame.

    Based on the datasheet this indicates that the two streams at the 954 Rx Ports are not synchronised or have some other incompatible differences

    I have configured the 954 GPIOs to output the FV and LV signals from each of the RX ports. This shows them to be aligned within a couple of microseconds.

    I have configured a GPIO to output the CSI-2 RX Ports Synchronised (Reg 0x12 -> 0x95).  But this is continuously low (in my previous post I indicated it was pulsing - but that was incorrect)

    I am unable to get the GPIO to change state for any of the options which use CSI-2 Tx Port as the Output Signal Source.  I would have expected Pass, FV or LV options to show activity.  Is there something I need to do to to get the CSI-2 Tx Port to activate these signals?

    Does FWD_STS (Reg 0x22) Bit 0 indicate if the Rx Ports are correctly synchronsed to allow synchronised forwarding?

    We observed that if one RX port is disabled then this bit is never set.  Which makes sense. However, when both ports are enabled then this bit is set whether or not the streams are synchronised.  We tested this both for the situation above where the streams are apparently closely sync'ed and when we allowed one of the sensors to freerun. In both cases the sync bit was asserted.

    We have noticed similar behaviour on the CSI-2 port.

    Can you make any recommendations as to how we can diagnose why the 954 will not properly forward to apparently sync'd video streams.

    Thanks

    Paul

  • 0 in reply to paulmcw
    TI__Genius 11340 points

    Hi Paul,

    I am unable to get the GPIO to change state for any of the options which use CSI-2 Tx Port as the Output Signal Source.  I would have expected Pass, FV or LV options to show activity.  Is there something I need to do to to get the CSI-2 Tx Port to activate these signals? Could you check if your CSI port is actually enabled? Register 0x33[0] should be set to 1.

    Does FWD_STS (Reg 0x22) Bit 0 indicate if the Rx Ports are correctly synchronsed to allow synchronised forwarding? Yes. This register should indicate whether or not the two sensors are synchronized. Could you provide a scopeshot of the two video streams and what it reads on 0x22?

    Best,

    Jiashow