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DS90UB941AS-Q1: check the initialization register and sequence requirements

Part Number: DS90UB941AS-Q1


Dear team,

The initialization register is as below, is there any problem? Do we have sequence requirements about the registers? Is this sequence right? Do I miss some information?

(0x03, 0xda)

(0x0E, 0x30)

(0x0F, 0x03)

(0x06, 0x58)

(0x07, 0x34)

(0x08, 0x34)

(0xC6, 0x21)

(0x4F, 0x0c)

(0x04, 0x90)

Thanks & Best Regards,

Sherry

  • Hello Sherry,

    Please share the details of your system setup. Without any details there is no way for us to know if your configuration is correct. Can you please share:

    - Deserializer and FPD link lanes (1 or 2)

    - DSI data rate 

    - Number of DSI lanes 

    - Intended 941AS clocking mode 

    - Any other relevant details to desired system configuration 

    Thanks,

    Casey 

  • Hi Casey,

    - Deserializer is 948 and 2 FPD link lanes 

    - DSI data rate is 100Mbps

    - Number of DSI lanes : 4

    - Intended 941AS clocking mode: external clock(>100MHz)

    When initializing registers, should I consider other conditions besides the above factors?

    Thanks & Best Regards,

    Sherry

  • - assuming you have continuous clock and dual dsi input

    0x5B = 0x03 #Dual FPD Link Mode

    0x1E = 0x01 #FPD Link Port 0 

    0x4F = 0xCC #(cont. clock 4 lanes) 

    0x1E = 0x02 #FPD Link Port 1 

    0x4F = 0xCC #(cont. clock 4 lanes) 

    # these registers are based on the input config you gave. 
    #######################################################################
    # these registers are based on the registers you wrote

    0x03, 0xda)

    (0x0E, 0x30)

    (0x0F, 0x03)

    (0x06, 0x58) #this field is autoloaded, no need to write

    (0x07, 0x34)

    (0x08, 0x34)

    (0xC6, 0x21)

    (0x4F, 0x0c)

    (0x04, 0x10) #enable packetized audio, don't write in the reserved field