This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMH1297: LMH1297 question consulting

Part Number: LMH1297
Other Parts Discussed in Thread: LMH0302

Hi; we  use LMH1297, have encountered some problems. Could you please give me some Suggestions,Thanks!

 A, LMH1297 use as equalizer, directly connected to the FPGA,when  input 6G signal,  PFGA can  recognize & work properly; But when 12G  signal input, PFGA can not  recognize properly,Currently there is no 12G test equipment, Cannot test the LMH1297 output signal,Could you help check the schematic diagram &PCB? or need to change the configuration of LMH1297?

  

 B ,LMH1297 use as Driver;the eye diagramis normal when HD/3G HD output. But when  Output SD Video Singal,the rising edge of  eye diagramis is about100PS;Required value 400 ~ 1500 ps;Similar to LMH0302, it has SD/HD selection pin .Does LMH1297 have similar functions (registers) for configuration selection? Thanks!

  • Greetings,

    To debug this, it may be easier if we start with cable driver side. At SD, you should be able to get SMPTE compatible eye diagram with greater than 400ps and less than 1.5ns rise/fall time. Something doesn't look right. To put the device in cable driver mode with minimized settings, please do the followings:

    1). Please make sure OUT0_SEL and SDI_OUT_SEL are floating(no connection).

    2). Please make sure OUT_CTRL, ENABLE, SDI_VOD, and HOST_EQ0 all are floating(no connection).

    3). There is no need for R104 and R104. Please un-install these resistors.

    4).  Please pull EQ/CD_SEL high through 1K ohm Resistor to VIN(2.5V)

    After these settings, device is setup for cable driver mode.

    A). Apply SD signal on IN0+/-

    B). First make sure LOCK_N is asserted(note LOCK_N is 3.3V tolerant and you may need to reduce your 1K ohm resistor to 200 ohm).

    Before we go further, please make sure LOCK_N is asserted(it is low). Once LOCK_N is low or asserted, you should see a valid SD output eye diagram. Please go through these and let us know.

    Regards,, Nasser