DP83620: Receive error occurs on Rx board after reset the clock input(X1) on Tx board, why?

Hi,

What do you mean "Reset the clock input (X1)"?

X1 clock must be stable before the hard-reset. See section "4.6 AC Specifications - Reset Timing" for more details.

Regards,

Hung Nguyen

Hi,

As mentioned in earlier post, the XI clock must be stable at least 1us before the hardware reset. If the XI clock comes after the hardware reset is released, the PHY could be in unknown state.

If the hardware reset signal is also from FPGA, you can delay it >1us before releasing it, assuming the clock from FPGA to the PHY will be stable within 1us.

Regards,

Hung Nguyen

Thanks Hung 

I think you might misunderstand my point. Maybe I didn't make it clear enough.

The first question is:

1) After power up, everything is ok. Then I push the reset button to reset FPGA on Master board which will also reset clock which connect to X1 of DP83620 on Master board. These are done on Master board and nothing else were done besides that. I also didn't hard reset PHY.

Then the Slave board which connect with Master board has receive errors. Why?  From your point, I think it is because the reset of X1 will cause the PHY  in unknown state. Is that right?

2)Then I hardreset the PHY on slave board(Pay attention: Not on Master board. I never hard reset PHY on Master board.). After that, everything is ok and no errors again. Why? I don't know why and need your further expanation.

Thank you very much!

Hi Weili,

Here is my explanation:

1) When you reset the FPGA, the clock to XI of DP83620 will be gone for some time. Without reference clock, DP83620 PHY will be in unknown state. The device can send out garbage signal which might choke up the Slave board. We cannot guarantee the PHY operation in this illegal condition. If the clock is reset, it needs to be followed by a hardware reset.

2) As mentioned above, the Slave board might be in lockup condition as it sees garbage signal from the Master board when the clock is reset. So, hardware reset can bring it out of lockup state. In your earlier post, unplugging and plugging back the cable can also bring it back to normal operation, which is expected as unplugging the cable basically resets the PHY's state and it starts a new linkup process.

Hope it helps!

Hung Nguyen 

Hi,Hung

Thank you very much for your reply.

One last question:

I also have a board which use PHY chip 88E1512 of Marvell. It didn't have this problem when I reset the master board. Can it say that 88E1512 can't be affected by X1 while DP83620 will be affected? Do they have different mechanism for comminication?

Thanks again.