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DP83867IS: SGMII clock regenerate internal timing

Peter Soerensen
Prodigy 60 points

Part Number: DP83867IS

The data sheet states SEtup and hold time of 100pS. The period time is 800pS. From this you cold wrongly conclude that the data eye need only be 200pS.

However the SGMII clock is internal regenerated from the data. There is a jitter specification for SGMII clock output pin but this do not tell anythink about the internatl regenerated jitter. So my question i how must is internal SGMII clock jitter (when the input signal has a lot of jitter) or how small can the SGMII data eye be and the input will still work?

  • 0
    TI__Mastermind 18425 points

    Hi Peter,

    We do not specific input SGMII clock jitter since the input clock is recovered from SGMII data. We test the PHY by using a SGMII signal with max allowed jitter as the test input and verify that the PHY can still communicate correctly. So as long as the SGMII input to the PHY complies to the SGMII standard, the PHY should be able communicate correctly.

    -Regards

    Aniruddha

  • 0 in reply to Aniruddha Khadye
    Prodigy 60 points

    I see, then I would very must like to know what is the max allowed jitter on SGMII, aas I have not been able to find this?

  • 0 in reply to Peter Soerensen
    TI__Mastermind 18425 points

    Hi Peter,

    We can support max input Total jitter of 0.75UI(600ps) for upto 6MHz jitter frequency. Around 6MHz we observe a knee and the input tolerance starts gradually reducing to about 0.1UI(80ps) at 100MHz jitter frequency. Since this is not characterized for datasheet, I would recommend using these numbers as reference and if input jitter is a critical parameter then perform some system level tests to verify that the Ethernet sub-system works as expected. There isn't really a guidance on the SGMII input jitter tolerance in the spec document, so apologies for creating confusion on that note.

    -Regards

    Aniruddha