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DP83867IS: TI PHY SGMII clock output stops after 20 seconds

Jeff Stutzman
Prodigy 75 points
Part Number: DP83867IS

I'm using the TI PHY part DP83867IS on a Xilinx VCU118 development board. I switch to 6-wire mode and then perform the software workaround for the RX_CTRL strap (reg 0x31 bit 7 to 0). My FPGA receives the 625 MHz differential clock for 20 seconds and then the clock input to the FPGA for the MAC appears to stops. I've investigated the SGMII IP core in the FPGA and can't find any issues. I can still talk via MDIO to the TI PHY just fine after the timeout. If I power down and back up the TI PHY (via registers) or perform a software reset then the clock starts back up again for 20 seconds. It is very consistently 20 seconds.  What could be causing this behavior? It almost seems like the TI part is in a sleep mode?  Is it expecting certain responses from the MAC in order to provide the clock?  Below is the MDIO register reads of the TI PHY and the Xilinx SGMII core - does anything jump out there? Thanks.

TI-PHY chip MDIO Read, PhyAddr: 3
------------------------------------------------------------
TI-PHY MDIO Addr: 0x000  0x00001140
TI-PHY MDIO Addr: 0x001  0x0000796d
TI-PHY MDIO Addr: 0x002  0x00002000
TI-PHY MDIO Addr: 0x003  0x0000a231
TI-PHY MDIO Addr: 0x004  0x000001e1
TI-PHY MDIO Addr: 0x005  0x0000cde1
TI-PHY MDIO Addr: 0x006  0x0000006d
TI-PHY MDIO Addr: 0x007  0x00002001
TI-PHY MDIO Addr: 0x008  0x00004006
TI-PHY MDIO Addr: 0x009  0x00000300
TI-PHY MDIO Addr: 0x00a  0x00003c00
TI-PHY MDIO Addr: 0x00b  0x00000000
TI-PHY MDIO Addr: 0x00c  0x00000000
TI-PHY MDIO Addr: 0x00d  0x0000401f
TI-PHY MDIO Addr: 0x00e  0x00000000
TI-PHY MDIO Addr: 0x00f  0x00003000
TI-PHY MDIO Addr: 0x010  0x00005841
TI-PHY MDIO Addr: 0x011  0x0000af02
TI-PHY MDIO Addr: 0x012  0x00000000
TI-PHY MDIO Addr: 0x013  0x00000000
TI-PHY MDIO Addr: 0x014  0x000029c7
TI-PHY MDIO Addr: 0x015  0x00000000
TI-PHY MDIO Addr: 0x016  0x00000000
TI-PHY MDIO Addr: 0x017  0x00000040
TI-PHY MDIO Addr: 0x018  0x00006150
TI-PHY MDIO Addr: 0x019  0x00004444
TI-PHY MDIO Addr: 0x01a  0x00000002
TI-PHY MDIO Addr: 0x01e  0x00000002
TI-PHY MDIO Addr: 0x01f  0x00000000
TI-PHY MDIO Addr: 0x025  0x00000400
TI-PHY MDIO Addr: 0x02d  0x00000000
TI-PHY MDIO Addr: 0x031  0x00001170
TI-PHY MDIO Addr: 0x032  0x00000000
TI-PHY MDIO Addr: 0x033  0x00000000
TI-PHY MDIO Addr: 0x037  0x00000000
TI-PHY MDIO Addr: 0x043  0x000007a0
TI-PHY MDIO Addr: 0x055  0x00000001
TI-PHY MDIO Addr: 0x06e  0x00000803
TI-PHY MDIO Addr: 0x06f  0x00000050
TI-PHY MDIO Addr: 0x0d3  0x00004000
TI-PHY MDIO Addr: 0x0dc  0x00003800
TI-PHY MDIO Addr: 0x0fe  0x0000e721
TI-PHY MDIO Addr: 0x134  0x00001000
TI-PHY MDIO Addr: 0x135  0x00000000
TI-PHY MDIO Addr: 0x170  0x00000c0f
TI-PHY MDIO Addr: 0x172  0x00000000

SGMII Core MDIO Read, PhyAddr: 5
------------------------------------------------------------
SGMII MDIO Addr: 0x00  0x00001140
SGMII MDIO Addr: 0x01  0x000001c8
SGMII MDIO Addr: 0x02  0x00000174
SGMII MDIO Addr: 0x03  0x00000c00
SGMII MDIO Addr: 0x04  0x00000001
SGMII MDIO Addr: 0x05  0x0000d801
SGMII MDIO Addr: 0x06  0x00000004
SGMII MDIO Addr: 0x07  0x00000000
SGMII MDIO Addr: 0x08  0x00000000
SGMII MDIO Addr: 0x0f  0x00008000
SGMII MDIO Addr: 0x10  0x00000003

TI-PHY chip MDIO Read, PhyAddr: 3
------------------------------------------------------------
TI-PHY MDIO Addr: 0x000  0x00001140
TI-PHY MDIO Addr: 0x001  0x0000796d
TI-PHY MDIO Addr: 0x002  0x00002000
TI-PHY MDIO Addr: 0x003  0x0000a231
TI-PHY MDIO Addr: 0x004  0x000001e1
TI-PHY MDIO Addr: 0x005  0x0000cde1
TI-PHY MDIO Addr: 0x006  0x0000006d
TI-PHY MDIO Addr: 0x007  0x00002001
TI-PHY MDIO Addr: 0x008  0x00004006
TI-PHY MDIO Addr: 0x009  0x00000300
TI-PHY MDIO Addr: 0x00a  0x00003c00
TI-PHY MDIO Addr: 0x00b  0x00000000
TI-PHY MDIO Addr: 0x00c  0x00000000
TI-PHY MDIO Addr: 0x00d  0x0000401f
TI-PHY MDIO Addr: 0x00e  0x00000000
TI-PHY MDIO Addr: 0x00f  0x00003000
TI-PHY MDIO Addr: 0x010  0x00005841
TI-PHY MDIO Addr: 0x011  0x0000af02
TI-PHY MDIO Addr: 0x012  0x00000000
TI-PHY MDIO Addr: 0x013  0x00000000
TI-PHY MDIO Addr: 0x014  0x000029c7
TI-PHY MDIO Addr: 0x015  0x00000000
TI-PHY MDIO Addr: 0x016  0x00000000
TI-PHY MDIO Addr: 0x017  0x00000040
TI-PHY MDIO Addr: 0x018  0x00006150
TI-PHY MDIO Addr: 0x019  0x00004444
TI-PHY MDIO Addr: 0x01a  0x00000002
TI-PHY MDIO Addr: 0x01e  0x00000002
TI-PHY MDIO Addr: 0x01f  0x00000000
TI-PHY MDIO Addr: 0x025  0x00000400
TI-PHY MDIO Addr: 0x02d  0x00000000
TI-PHY MDIO Addr: 0x031  0x00001170
TI-PHY MDIO Addr: 0x032  0x00000000
TI-PHY MDIO Addr: 0x033  0x00000000
TI-PHY MDIO Addr: 0x037  0x00000000
TI-PHY MDIO Addr: 0x043  0x000007a0
TI-PHY MDIO Addr: 0x055  0x00000001
TI-PHY MDIO Addr: 0x06e  0x00000803
TI-PHY MDIO Addr: 0x06f  0x00000050
TI-PHY MDIO Addr: 0x0d3  0x00004000
TI-PHY MDIO Addr: 0x0dc  0x00003800
TI-PHY MDIO Addr: 0x0fe  0x0000e721
TI-PHY MDIO Addr: 0x134  0x00001000
TI-PHY MDIO Addr: 0x135  0x00000000
TI-PHY MDIO Addr: 0x170  0x00000c0f
TI-PHY MDIO Addr: 0x172  0x00000000

(SGMII clock to FPGA now stopped!)

SGMII Core MDIO Read, PhyAddr: 5
------------------------------------------------------------
SGMII MDIO Addr: 0x00  0x00000000
SGMII MDIO Addr: 0x01  0x00000000
SGMII MDIO Addr: 0x02  0x00000000
SGMII MDIO Addr: 0x03  0x00000000
SGMII MDIO Addr: 0x04  0x00000000
SGMII MDIO Addr: 0x05  0x00000000
SGMII MDIO Addr: 0x06  0x00000000
SGMII MDIO Addr: 0x07  0x00000000
SGMII MDIO Addr: 0x08  0x00000000
SGMII MDIO Addr: 0x0f  0x00000000
SGMII MDIO Addr: 0x10  0x00000000

  • 0
    TI__Mastermind 18425 points

    Hi Jeff,

    Do you try reading the PHY registers after you notice that the SGMII output clock is off? Can you share those as well? Do you see any other signs that the PHY has entered power down mode?

    -Regards

    Aniruddha

  • 0 in reply to Aniruddha Khadye
    Prodigy 75 points

    Here is the TI Ethernet PHY read just after the SGMII read (after the clock has appeared to stop).

    I don't see any other indications that the TI PHY is powered down.  Could it be related to the software workaround for the RX_CTRL strapping (register 0x31)?

    Thanks for the help!

    TI-PHY chip MDIO Read, PhyAddr: 3
    ------------------------------------------------------------
    TI-PHY MDIO Addr: 0x000  0x00001140
    TI-PHY MDIO Addr: 0x001  0x0000796d
    TI-PHY MDIO Addr: 0x002  0x00002000
    TI-PHY MDIO Addr: 0x003  0x0000a231
    TI-PHY MDIO Addr: 0x004  0x000001e1
    TI-PHY MDIO Addr: 0x005  0x0000cde1
    TI-PHY MDIO Addr: 0x006  0x0000006d
    TI-PHY MDIO Addr: 0x007  0x00002001
    TI-PHY MDIO Addr: 0x008  0x00004006
    TI-PHY MDIO Addr: 0x009  0x00000300
    TI-PHY MDIO Addr: 0x00a  0x00003c00
    TI-PHY MDIO Addr: 0x00b  0x00000000
    TI-PHY MDIO Addr: 0x00c  0x00000000
    TI-PHY MDIO Addr: 0x00d  0x0000401f
    TI-PHY MDIO Addr: 0x00e  0x00000000
    TI-PHY MDIO Addr: 0x00f  0x00003000
    TI-PHY MDIO Addr: 0x010  0x00005841
    TI-PHY MDIO Addr: 0x011  0x0000af02
    TI-PHY MDIO Addr: 0x012  0x00000000
    TI-PHY MDIO Addr: 0x013  0x00000000
    TI-PHY MDIO Addr: 0x014  0x000029c7
    TI-PHY MDIO Addr: 0x015  0x00000000
    TI-PHY MDIO Addr: 0x016  0x00000000
    TI-PHY MDIO Addr: 0x017  0x00000040
    TI-PHY MDIO Addr: 0x018  0x00006150
    TI-PHY MDIO Addr: 0x019  0x00004444
    TI-PHY MDIO Addr: 0x01a  0x00000002
    TI-PHY MDIO Addr: 0x01e  0x00000002
    TI-PHY MDIO Addr: 0x01f  0x00000000
    TI-PHY MDIO Addr: 0x025  0x00000400
    TI-PHY MDIO Addr: 0x02d  0x00000000
    TI-PHY MDIO Addr: 0x031  0x00001170
    TI-PHY MDIO Addr: 0x032  0x00000000
    TI-PHY MDIO Addr: 0x033  0x00000000
    TI-PHY MDIO Addr: 0x037  0x00000000
    TI-PHY MDIO Addr: 0x043  0x000007a0
    TI-PHY MDIO Addr: 0x055  0x00000001
    TI-PHY MDIO Addr: 0x06e  0x00000803
    TI-PHY MDIO Addr: 0x06f  0x00000050
    TI-PHY MDIO Addr: 0x0d3  0x00004000
    TI-PHY MDIO Addr: 0x0dc  0x00003800
    TI-PHY MDIO Addr: 0x0fe  0x0000e721
    TI-PHY MDIO Addr: 0x134  0x00001000
    TI-PHY MDIO Addr: 0x135  0x00000000
    TI-PHY MDIO Addr: 0x170  0x00000c0f
    TI-PHY MDIO Addr: 0x172  0x00000000

  • 0 in reply to Jeff Stutzman
    TI__Mastermind 18425 points

    Hi Jeff,

    Can you try writing 0x5048 to register 0x10?

    If you bypass the write operation to register 0x31, does the SGMII stay on?

    What is the 25MHz clock source connected on XI pin of the PHY? If its a crystal can you share that crystal schematics and part number?

    When you run into this issue, can you measure the voltage on on supply pins, across RBIAS pin and ground, and probe the Reset pin to check that the process is not putting the PHY in reset.

    -Regards

    Aniruddha 

  • 0 in reply to Aniruddha Khadye
    Prodigy 75 points

    Thanks for the reply.

    Here are my responses:

    - writing 0x5048 to register 0x10 results in no clock to the SGMII IP core in the FPGA (I think that is because bit 11 is low which is disabling the SGMII mode in the PHY)

    - bypassing register 0x31 also results in no clock to the SGMII IP - i think the SW workaround is required here

    - XI pin is connected to a 25 MHz clock from Abracon XTAL_ABM8 (p/n 535-9140-2-ND) osc.  This is from the Xilinx VCU118 dev board REV2.0 schematic.

    - I'll need to see if I can access these pins for a measurement

    Jeff

  • 0 in reply to Jeff Stutzman
    Prodigy 75 points

    We received a second FPGA development board.  I ran the same bitfiles and setup/config scripts - the ethernet worked correctly.  SGMII clock stays constant coming into the FPGA and I was able to fully receive Ethernet frames from the FPGA.  This points to some defect or potential hardware issue on our original board.  Thanks for the help!