DS90UH947-Q1: PCLK bit going high without PCLK being applied

Hi Casey,

Thank you for the insight! A few additional questions related to PCLK detect..

1. How long does PCLK need to exist/be present before pclk is set?
2. How consistent does the frequency need to be for the pclk detect bit to be set?
3. How large of a frequency change does the serializer need to detect before resetting the FPD3 PLL?
4. How long would it take for the serializer to detect a change in pclk frequency?

Thank you,

Jared

Hi Casey,

Got it, thanks! One more question.. does the PCLK detect wait for the OLDI clock to interface with the PLL inside the chip before the bit is flipped to "1" or does it flip to "1" immediately when the OLDI clock reaches the inside of the chip?

Thanks,

Jared

Hi Casey,

Ok, so it sounds like this circuit and detection is independent of the PLL, correct? Do you know how many pixel clock edges the circuit has to see in the 4us period to determine that a proper PCLK is there?

Thanks,

Jared

Thanks Casey,

When you say measurements are updated every 10us, what do you mean by that? Is there a register that gets updated with the specific PCLK frequency that is derived from this counter?

Best,

Jared

Hey Jared, 

Yes, register 0x57

Best Regards,

Casey 

Hi Casey,

Register 0x57 on the UH947 datasheet is for TDM configuration..

-Jared