• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 33 subscribers
  • Views 550 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

slk 2501 clock problem

Nikola Vranic
Prodigy 130 points

Hello,

I have design like on picture and all what I want is to make loop thourgh FPGA.

Problem is that I have 1 oscillator for each slk2501 chip which are slightly different (clk 2 - clk 1 =~ 11 Hz for STM1, and ~1MHz for STM4)  which result empty or full FIFO in FPGA.

Please, how to setup TX and RX clk for each slk 2501 chip? I try few cases but we just cann't make it to work. How to setup LCKREFN and LOOPTIME signals?

Best regards,

Nikola

 

  • 0
    TI__Intellectual 1810 points

    Hi Nikola,

    The TXCLKSRC1 from the SLK2501_number_1 should be used by the FPGA to send back data to the SLK2501_number_1.  The TXCLKSRC2 from the SLK2501_number_2 should be used by the FPGA to send back data to the SLK2501_number_2. Please also note that TXCLKSRC is not the same as RXCLK. TXCLKSRC is frequency-locked to the local reference clock (REFCLK) while RXCLK is the recovered clock. RXCLK is frequency-locked to REFCLK only when LOCKREFN is set low which you don't want to do if you're receiving serial data from a remote source.

    LOOPTIME when set high makes the device send serial output on STXDOP/N using the recovered clock. 

    By the way, what's the source of the reference clock for the FPGA?

    Best regards.

    Hassan.