DS110DF1610: DS110DF1610 lock issue

AndongSun

Part Number: DS110DF1610
Other Parts Discussed in Thread: DS125DF1610

Hi expert:

My customer use DS110DF1610 for conversion card. The schematic diagram of our product is as follows:

Because some cards can be locked, but some cards can not be locked. Later the cards were modified to not use cross point and not to use the manually set rate, the result is the same as before.

Attached is the chip initialization program, the debugging information of cards that cannot be locked and debugging information of the cards that can be locked .

Fullscreen Ds110DF1610.c Download

void ds110df1610_init(unsigned char card_type, unsigned char sw, unsigned char work_mode)
{
	unsigned char regvalue = 0, i = 0;
	unsigned char low, high;
	unsigned int val;
	rt_thread_delay(200);// wait chip ready, old is 50
	i2c_lock();
	regvalue = 0x00;
	i2c_write_ds280df810(0xff, &regvalue);//select shared 
	i2c_read_ds280df810(0x01,&regvalue);//high 3bit device verion, low 5 bit device id
	rt_kprintf("dev info = 0x%02x (high 3bit device version, low 5 bit device id)\r\n", regvalue);
	i2c_read_ds280df810(0xfe,&regvalue);
	rt_kprintf("vendor id = 0x%02x (expect 0x03)\r\n",regvalue);
	regvalue = 0x00;
	i2c_write_ds280df810(0x02, &regvalue);//Sets the REFCLK input frequency as 25M
	i2c_write_ds280df810_withmask(0x0B, 0x10, 0x10);//single-ended input
	i2c_write_ds280df810_withmask(0x05, 0x08, 0x0f);//sets max number of channels that can lock at any given time.
	//i2c_write_ds280df810_withmask(0xff, 0x00, 0x03);//select shared 
	//i2c_write_ds280df810_withmask(0x02, 0x00, 0x60);//Sets the REFCLK input frequency as 25M
	//i2c_write_ds280df810_withmask(0x0B, 0x10, 0x10);//single-ended input
	
	i2c_write_ds280df810_withmask(0xff, 0x01, 0x03);//select channel 
	regvalue = 0;
	i2c_write_ds280df810(0xfd, &regvalue);
	rt_kprintf("rate = 0x%02x;work_mode = 0x%02x\r\n",sw,work_mode);
	for(i = 0; i < 4; i++){
		regvalue = (1<<i);
		i2c_write_ds280df810(0xfc, &regvalue);
		i2c_write_ds280df810_withmask(0x0, 0x04, 0x04);//reset channel register to power-on default values
		i2c_write_ds280df810_withmask(0xa, 0x0c, 0x0c);//assert CDR reset
		//TBD
		//set rate, more rate programming, refer to page 68, the section 7.2.2 Data Rate Selection (Manual Programming)
		i2c_write_ds280df810_withmask(0x2f, 0xc0, 0xf0);//set rate as 10.3125Gbps		
		//adapt mode
		i2c_write_ds280df810_withmask(0x31, 0x60, 0x60);//adapt mode1:only CTLE
		//i2c_write_ds280df810_withmask(0x31, 0x0, 0x60);//no adapt
		//i2c_write_ds280df810_withmask(0x31, 0x40, 0x60);//adapt mode2
		//i2c_write_ds280df810_withmask(0x31, 0x60, 0x60);//adapt mode3
		//i2c_write_ds280df810_withmask(0x1e, 0x08, 0x0a);//disable dfe ?
		i2c_write_ds280df810_withmask(0x1e, 0x08, 0x08);//enable dfe ?
		i2c_write_ds280df810_withmask(0x3d, 0x00, 0x80);//enable fir   ?
		i2c_write_ds280df810_withmask(0x3d, 0x0, 0x40);//main-cursor tap sign to positive
		i2c_write_ds280df810_withmask(0x3f, 0x40, 0x40);//post-cursor tap sign to negative
		i2c_write_ds280df810_withmask(0x3e, 0x40, 0x40);//pre-cursor tap sign to negative
		i2c_write_ds280df810_withmask(0x3d, 0x0c, 0x3f);//main-cursor tap magnitude
		i2c_write_ds280df810_withmask(0x3f, 0x0, 0x3f);//post-cursor tap magnitude
		i2c_write_ds280df810_withmask(0x3e, 0x0, 0x3f);//pre-cursor tap magnitude
		i2c_write_ds280df810_withmask(0x0a, 0x00, 0x0c);//release CDR reset
	}
	
	for(i = 4; i < 8; i++){
		regvalue = (1<<i);
		i2c_write_ds280df810(0xfc, &regvalue);
		i2c_write_ds280df810_withmask(0x15, 0x18, 0xff);//Power down the driver
		i2c_write_ds280df810_withmask(0x14, 0x44, 0xff);//Force signal detect status to 0
		i2c_write_ds280df810_withmask(0x13, 0xf0, 0xff);//Power down signal detect block
	}
	
	regvalue = 0;
	i2c_write_ds280df810(0xfc, &regvalue);
	for(i = 0; i < 8; i++){
		regvalue = (1<<i);
		i2c_write_ds280df810(0xfd, &regvalue);
		i2c_write_ds280df810_withmask(0x15, 0x18, 0xff);//Power down the driver
		i2c_write_ds280df810_withmask(0x14, 0x44, 0xff);//Force signal detect status to 0
		i2c_write_ds280df810_withmask(0x13, 0xf0, 0xff);//Power down signal detect block
	}
	i2c_unlock();

	//set_board_rate(4,sw);

}

Fullscreen debug information of card that can be locked.txt Download

�����߿�Ҳ������SFP1(RX0A)��SFP4��RX1A�����������ĸ�ͨ���ĵ�����Ϣ��
finsh>>show_cdr()                                                               
Horizontal and Vertical Eye:HEO_UI=val/32,VEO_mV=val*3.125                      
CH 0:                                                                           
HEO_UI=21 ,VEO_mV=62                                                            
CTLE boost value=2                                                              
Status reg[0x78]=0x30[5:SD,4:LCK]                                               
ch reg[0x31]=0x60, bit6:5-adapt mode                                            
adapt3:CTLE until lock,then dfe,the eq                                          
ch reg[0x1e]=0xe9, bit3-DFE switch                                              
DFE disable                                                                     
Main:0xc[6:Sign,5-0:mag]                                                        
Post:0xc0[6:Sign,5-0:mag]                                                       
Pre:0x40[6:Sign,5-0:mag]                                                        
CH 1:                                                                           
HEO_UI=0 ,VEO_mV=0                                                              
CTLE boost value=165                                                            
Status reg[0x78]=0x0[5:SD,4:LCK]                                                
ch reg[0x31]=0x60, bit6:5-adapt mode                                            
adapt3:CTLE until lock,then dfe,the eq                                          
ch reg[0x1e]=0xe9, bit3-DFE switch                                              
DFE disable                                                                     
Main:0xc[6:Sign,5-0:mag]                                                        
Post:0xc0[6:Sign,5-0:mag]                                                       
Pre:0x40[6:Sign,5-0:mag]                                                        
CH 2:                                                                           
HEO_UI=25 ,VEO_mV=70                                                            
CTLE boost value=0                                                              
Status reg[0x78]=0x30[5:SD,4:LCK]                                               
ch reg[0x31]=0x60, bit6:5-adapt mode                                            
adapt3:CTLE until lock,then dfe,the eq                                          
ch reg[0x1e]=0xe9, bit3-DFE switch                                              
DFE disable                                                                     
Main:0xc[6:Sign,5-0:mag]                                                        
Post:0xc0[6:Sign,5-0:mag]                                                       
Pre:0x40[6:Sign,5-0:mag]                                                        
CH 3:                                                                           
HEO_UI=0 ,VEO_mV=0                                                              
CTLE boost value=165                                                            
Status reg[0x78]=0x0[5:SD,4:LCK]                                                
ch reg[0x31]=0x60, bit6:5-adapt mode                                            
adapt3:CTLE until lock,then dfe,the eq                                          
ch reg[0x1e]=0xe9, bit3-DFE switch                                              
DFE disable                                                                     
Main:0xc[6:Sign,5-0:mag]                                                        
Post:0xc0[6:Sign,5-0:mag]                                                       
Pre:0x40[6:Sign,5-0:mag]                                                        
        0, 0x00000000

Fullscreen debug information of card that can not be locked.txt Download

�����߿�������SFP1(RX0A)��SFP4��RX1A�����������ĸ�ͨ���ĵ�����Ϣ��
finsh>>show_cdr()                                                               
Horizontal and Vertical Eye:HEO_UI=val/32,VEO_mV=val*3.125                      
CH 0:                                                                           
HEO_UI=0 ,VEO_mV=0                                                              
CTLE boost value=165                                                            
Status reg[0x78]=0x20[5:SD,4:LCK]                                               
ch reg[0x31]=0x60, bit6:5-adapt mode                                            
adapt3:CTLE until lock,then dfe,the eq                                          
ch reg[0x1e]=0xe9, bit3-DFE switch                                              
DFE disable                                                                     
Main:0xc[6:Sign,5-0:mag]                                                        
Post:0xc0[6:Sign,5-0:mag]                                                       
Pre:0x40[6:Sign,5-0:mag]                                                        
CH 1:                                                                           
HEO_UI=0 ,VEO_mV=0                                                              
CTLE boost value=165                                                            
Status reg[0x78]=0x0[5:SD,4:LCK]                                                
ch reg[0x31]=0x60, bit6:5-adapt mode                                            
adapt3:CTLE until lock,then dfe,the eq                                          
ch reg[0x1e]=0xe9, bit3-DFE switch                                              
DFE disable                                                                     
Main:0xc[6:Sign,5-0:mag]                                                        
Post:0xc0[6:Sign,5-0:mag]                                                       
Pre:0x40[6:Sign,5-0:mag]                                                        
CH 2:                                                                           
HEO_UI=0 ,VEO_mV=0                                                              
CTLE boost value=165                                                            
Status reg[0x78]=0x20[5:SD,4:LCK]                                               
ch reg[0x31]=0x60, bit6:5-adapt mode                                            
adapt3:CTLE until lock,then dfe,the eq                                          
ch reg[0x1e]=0xe9, bit3-DFE switch                                              
DFE disable                                                                     
Main:0xc[6:Sign,5-0:mag]                                                        
Post:0xc0[6:Sign,5-0:mag]                                                       
Pre:0x40[6:Sign,5-0:mag]                                                        
CH 3:                                                                           
HEO_UI=0 ,VEO_mV=0                                                              
CTLE boost value=165                                                            
Status reg[0x78]=0x0[5:SD,4:LCK]                                                
ch reg[0x31]=0x60, bit6:5-adapt mode                                            
adapt3:CTLE until lock,then dfe,the eq                                          
ch reg[0x1e]=0xe9, bit3-DFE switch                                              
DFE disable                                                                     
Main:0xc[6:Sign,5-0:mag]                                                        
Post:0xc0[6:Sign,5-0:mag]                                                       
Pre:0x40[6:Sign,5-0:mag]                                                        
        0, 0x00000000

Please help to analyze what causes the failure of locking and explain the process of chip locking.Any advice will be apprreciated.

Best regards

over 6 years ago

0 Rodrigo Natal over 6 years ago

TI__Mastermind 19235 points

Hi,

My initial debug suggestions are below:

It appears that retimer Rx adapt mode 3 is being used. I would recommend to try adapt mode 2
Recommend to set the DF1610 FIR pre-cursor and post-cursor weights both to zero

The retimer eye opening results look poor for the "CDR locked" case. At this point I speculate the Tx and/or Rx link settings are not optimized.

Regards,

Rodrigo Natal

HSSC Applications Engineer

0 user6016611 over 6 years ago in reply to Rodrigo Natal

Prodigy 190 points

After modifying the VGA parameters, the line card can already be locked.

Another issue is how long it takes for the signal to lock. Because the line card needs to switch channel to relock in protected mode.

0 Rodrigo Natal over 6 years ago in reply to user6016611

TI__Mastermind 19235 points

Hi,

For its default CDR reference mode, the max DS125DF1610 CDR lock time is 100ms.

Regards,

Rodrigo Natal

HSSC Applications Engineer

0 user6016611 over 6 years ago in reply to Rodrigo Natal

Prodigy 190 points

The line card is applied in protected mode as shown above, The active ports of the two cards are the same (for example: the sfp2 port is the active port and the sfp3 port is the backup port). When the sfp2 port becomes link down, the active port switches to the sfp3 port (the response time is approximately 10ms). From the test results of the tester, the switching time is about 1 second. We expect to switch over within 20ms.

0 Rodrigo Natal over 6 years ago in reply to user6016611

TI__Mastermind 19235 points

Hi,

The TI retimer CDR lock time may be reduced significantly by setting its eye opening based CDR lock thresholds to zero. With this setting the typical CDR lock time should be less than 10ms.To set the HEO and VEO lock thresholds to zero the host simply needs to set retimer channel register 0x6A = 0x00.

6A	7	0	RW	Y	VEO_LCK_THRSH3	VEO threshold to meet before lock is established. The LSB step size is 4 counts of VEO.
	6	0	RW	Y	VEO_LCK_THRSH2
	5	1	RW	Y	VEO_LCK_THRSH1
	4	0	RW	Y	VEO_LCK_THRSH0
	3	0	RW	Y	HEO_LCK_THRSH3	HEO threshold to meet before lock is established. The LSB step size is 4 counts of HEO.
	2	0	RW	Y	HEO_LCK_THRSH2
	1	1	RW	Y	HEO_LCK_THRSH1
	0	0	RW	Y	HEO_LCK_THRSH0

Cordially,

Rodrigo Natal

HSSC Applications Engineer

0 user6016611 over 6 years ago in reply to Rodrigo Natal

Prodigy 190 points

After setting the 0x6a register to 0x0, the APS switching time(CDR lock time) is reduced, but this time is still greater than 500ms.

0 Rodrigo Natal over 6 years ago in reply to user6016611

TI__Mastermind 19235 points

Hi,

How is the CDR lock time being measured exactly? TI have validated this timing parameter extensively and have full confidence that lock time is 100ms for default settings and < 10ms when HEO/VEO lock thresholds are set to zero.

Cordially,

Rodrigo Natal

HSSC Applications Engineer

0 user6016611 over 6 years ago in reply to Rodrigo Natal

Prodigy 190 points

When the line card application in protected mode, how should the cross point switch be configured(0x96 and 0x9b register).

0 user6016611 over 6 years ago in reply to Rodrigo Natal

Prodigy 190 points

When the line card application in monitor mode, how should the cross point switch be configured(0x96 and 0x9b register).

0 Rodrigo Natal over 6 years ago in reply to user6016611

TI__Mastermind 19235 points

Hi,

Please provide your email address and I can directly email you the TI programming guide document containing the DS125DF1610 cross-point configuration instructions.

Cordially,

Rodrigo Natal

HSSC Applications Engineer

0 user6016611 over 6 years ago in reply to Rodrigo Natal

Prodigy 190 points

Hi,

My email is benhua.gu@firstmile.com.cn. Thanks.

0 user6016611 over 6 years ago in reply to Rodrigo Natal

Prodigy 190 points

Hi,

Please help guide the cross point switch when it comes to protection mode and monitoring mode.

In addition, the switch is connected to the port, but the state of the CDR sometimes fails to detect the optical signal status(reg:0x78).

My email is benhua.gu@firstmile.com.cn

Thanks.

0 Rodrigo Natal over 6 years ago in reply to user6016611

TI__Mastermind 19235 points

Hi,

I've emailed you the programming guide directly.

I'm not sure why the retimer would not assert signal detect when presented with a valid signal. All of TI's validation test results show consistent signal detect assertion when input signal is above the threshold specified in the product datasheet.

Cordially,

Rodrigo Natal

HSSC Applications Engineer

0 user6016611 over 6 years ago in reply to Rodrigo Natal

Prodigy 190 points

Hi, Rodrigo Natal

Channel lock is related to those parameter settings?

Regards,

Benhua Gu

0 Rodrigo Natal over 6 years ago in reply to user6016611

TI__Mastermind 19235 points

Hi, see below inputs related to parameters gating retimer CDR locking.

If signal detect is not asserted, the retimer channel will not be allowed to lock. The user may however force signal detect high by setting channel register 0x14[7]=1
A CDR rate setting that matches the input data rate in question is required in order for the CDR to lock
Eye opening values also gate CDR lock. These thresholds may be adusted via channel register 0x6A
The Single Bit Transition function gates CDR lock. This function prevents CDR lock when transition density does not meet a minimum threshold. it may be disabled by setting 0x0C[3]=0

Cordially,

Rodrigo Natal

HSSC Applications Engineer

0 user6016611 over 6 years ago in reply to Rodrigo Natal

Prodigy 190 points

Hi, Rodrigo Natal

If the channel is not locked, what is the signal output from this channel?

Thanks

Regards,

Benhua Gu

0 Rodrigo Natal over 6 years ago in reply to user6016611

TI__Mastermind 19235 points

Hi,

For default setting, if the retimer channel CDR is not locked its output will be muted (i.e. turned off)

Regards,

Rodrigo Natal

HSSC Applications Engineer

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DS110DF1610: DS110DF1610 lock issue