DS90UB934-Q1: DS90UB953-Q1 / DS90UB934-Q1 Backwards Compatibility Mode - HSYNC / VSYNC

I believe there is a problem pasting screenshots here, so I' ve attached the images below using insert media, hopefully.

Gated v1-v2 / Ungated:

Hello Berkay,

We need about one day to respond back with the info. Thank you for your patience.

Best Regards,

Casey 

Hello Casey,

Thank you for the information, are there any updates on the topic ? Thank you.

Kind Regards,

Berkay

Hello Berkay,

The device essentially treats FV and a VSYNC and LV as an HSYNC signal on the output. When the 953 is configured for DVP mode, the device computes these timings from the Frame Start (FS) and Frame End (FE) codes that are send in the MIPI short packet.

Hello Mostafa,

Thank you for your answer, however I would like to clarify few things, to understand it better, if you allow. Should I expect a timing diagram like below diagrams on HSYNC/VSYNC outputs from DS90UB934-Q1, or will there be any delays/changes due to the internal gates/circuitry e.g. ? I would really appreciate if you have a clear timing diagram on this, thank you.

Horizontal Sync (HSYNC):

• Does DS90UB934-Q1 outputs HSYNC signal line with logic 0 level upon the Line End(LE) information in the MIPI frame until the Line Start(LS) and then does it outputs logic 1 level until the next Line End(LE) information ?

Vertical Sync (VSYNC):

• Does DS90UB934-Q1 outputs VSYNC signal line with logic 0 level upon the Frame End(FE) information in the MIPI frame until the Frame Start(FS)and then does it outputs logic 1 level until the next Frame End(FE) information ?

Kind Regards,

Berkay

Hi Berkay,

I am still confirming this. Thank you for your patience.

Hi Mostafa,

Is there any updates on the topic ? Unfortunately I cannot continue with the design until I'll be able to verify this. Thank you for your understanding as well, looking forward to your reply.