Hello,
my customer has developed a proprietary source-synchronous interface (line topology) based on GBit - RGMII where each device has two DP83867. For being fully synchronous in all devices they are using the recovered clock of the first PHY for supplying the second one.
Now he is facing a problem regarding the forwarding of the TX_CTRL--> RX_CTRL within the two connected PHYs: very sporadic we can observe that the fix interval of our control signal is not the same before and after the two PHYs that connect our devices. The rising edge is one 125 MHz ClkCycle faster/slower than expected. Their understanding is that this results from a resynchronization within the PHYs during CTRL-low-phase and that this only occurs if the phaseshift between X_I and GTX_CLK has a deterministic offset.
So they have some questions:
Can you confirm that there is such a resynchronization that could cause our phenomenon?
If so, could you tell us which exact phase-shift is critical (we think there are different internal delays as in error case the phases were not exactly identical)?
Is there any possibility to force the PHY not to resynchronize during CTRL-low-phase but to forward all incoming data (we could activate this feature if we are sure the PHYs have synchronized and are in phase)?
