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DS90UB926QSEVB: DS90UB926 to DS90UR905 connection.

Part Number: DS90UB926QSEVB
Other Parts Discussed in Thread: ALP, DS90UB926Q-Q1

Hi TI team.

The DS90UB926EVM and DS90UR905 are connected as shown below.

The ALP recognizes the DS90UR905 as a DS90UH925.

1. Is something wrong with this? or Is it working normally?

2. When testing the DS90UB926EVM alone, running the ALP pattern generator produces no data output. If it works normally, should the data be output?

Please check my Question.

Thanks,

Downey.

  • Kim,

    it sounds you have two issues here, please check below comments:

    1. regarding the connection between UR905 and UB926, pls check 926 d/s on the back-compatible design (section 8.3.3)

    8.3.3 Backward-Compatible Mode
    The DS90UB926Q-Q1 is also backward-compatible to DS90UR905Q and DS90UR907Q FPD Link II serializers
    at 15- to 65-MHz pixel clock frequencies. It receives 28 bits of data over a single serial FPD-Link II pair operating
    at the line rate of 420 Mbps to 1.82 Gbps. This backward-compatible mode is provided through the MODE_SEL
    pin (Table 9) or the configuration register (Table 11). In this mode, the minimum PCLK frequency is 15 MHz.

    2. for the UB926's internal pattern generation, you need use the internal timing mode as the ur905 maybe has no data to the 926 in your system.

    regards,

    Steven

  • Hi Steven,

    Thanks your support.

    I have one more question. 

    According to the LCD datasheet, the cycles of VS and HS are different.

    However, the HS and VS of the DS90UB926 are output in the same cycle. is it normal operation?

    Regards,

    Downey.

  • Downy,

    Certainly the VS is different from the HS. VS cycle includes the line counts plus the blanking in one video frame, and HS includes the line length plus blanking. this is shown in your above figure 3-4.

    If you get the same cycle of VS and HS signals, it means it has some problems here, maybe the VS and HS pin are connected together?

    best regards,

    Steven