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DP83848I: Question about the MII Transmit DP83848N

Vickers
Intellectual 980 points
Part Number: DP83848I

Hello,

When we recently tested the timing specifications of the MII interface, we found that the MII Transmit Timing of the DP83848N has an index requirement that the TXD setup time is greater than 10 ns. However, the IEEE Std 802.3-2005 standard only defines the TX characteristics of the MAC, and requires the TXD output delay to be 0-25 ns. The CPU (MAC) we use also conforms to this standard. However, the 10 ns requirement of the DP83848N cannot be met when the waveform setup time indicator is tested on the DP83848 N terminal.
I would like to ask:
1. Does the 10 ns minimum requirement of the DP83848N specification deviate from the standard?
2. How should we test the DP83848N setup time indicator?

  • 0
    TI__Mastermind 26320 points

    Hi,

    DP83848 PHY MII Interface needs stabilized data  when the Clock is transitioning. With 0 ns min, both data and clock  will transition together.

    Min of 10 ns is MII TX_CLK to TX_D0 spec for all TI PHYs.

    Regards,

    Geet

  • 0 in reply to Geet Modi
    Intellectual 980 points

    Hi Geet,

    We don't understand.

    According to the standard, in the MII mode, TX_CLK is sent by the PHY to the MAC, and the TXD of the MAC is delayed by Tov (0ns-25ns). For example, if the MAC outputs TXD after 2 ns, then the 10 ns requirement of the PHY cannot be met.